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TMS320C6678 : TIMER handling

Alban MICHELANGELI
Intellectual 270 points

Other Parts Discussed in Thread: TMS320C6678, TMS320C6672

Hello,

I currently use the TMS320C6678 for which I use the Timer TIMER0.

This timer is configured as described below :  

- TIMER0 configured in 32 bits timers  unchained mode without prescaler (Only TIMLO)

-  Enabling Mode set to 11b : enabled continuously with Reload

- Clock Source set to external Clock (signal on the timer pin TIMI0)

Wanted behavior is to call IRQ4 routine each time a rising edge occurs on the Timer pin. 

At the beginning, we configure TIMER0 period to 1.  But resulting behavior is an IRQ4 routine called "one time in two", due to the Timer counter reset

occuring only at the next timer imput clock cycle.

Setting the Timer counter and period together to Zero allow us to obtain the wanted behavior.

Could you please confirm this behavior is the wanted one, because I read in document SPRUGV5A (March 2012) concerrning Timer Handling at 

 §3.9.2 Timer Count = 0 and Timer Period = 0 (No Prescaler) that the Timer interrupt is not generated.

Then, could you please  confirm me that such behavior occurs also with TMS320C6672.

Note that we can't use GPIO interrupt as all GPIOs aree alrerady used.

Regards

Alban

  • 0
    TI__Guru**** 161600 points

    Hi,

    I think this should be expected.

    You say:

      

    Alban MICHELANGELI said:
    Wanted behavior is to call IRQ4 routine each time a rising edge occurs on the Timer pin. 

    And when configured in uncahined mode, Timer Count = 0, Timer Period = 0 (No Prescaler) and Continuous mode with reload (ENAMODE bits = 11b), the timer will OUTPUT will depend on the CP value: 
     

       CP = 0 => PULSE mode: "The timer output pulses once at the first timer clock cycle, and the timer continues to count up. Whenever the timer counter reaches its maximum value, it rolls around to 0 (see Section 3.9.4), generating another pulse. The pulse width is defined by the PWID bits of the timer control register. The period registers are loaded with the reload registers"

       CP = 1 => CLOCK mode: "The timer output toggles once at the first timer clock cycle and then toggles with a frequency of half the timer clock frequency as the timer continues to count. The period registers are loaded with the reload registers." 

    The timer will output pulses on both cases (CP= 0  and CP = 1), so you will have RISING edges occurring on the timer pin, from here depending on how you call the IRQ it is possible to get interrupts. 

    However, I will ask the designers to correct/confirm my statement.

    Best Regards, 

    Yordan   

  • 0 in reply to Yordan Kovachev
    Intellectual 270 points
    Hi Yordan,

    Thanks for your quick answer.

    In fact, the software don' use the Timer Output Pin (TOUTLx).

    Wanted behavior is an IRQ4 interrupt gheneration when a rsisng edge occurs on Timer Input Pin (TINPLx).

    That's the found behavior with the Counter and Period set to 0 for TIMER0.

    Could you please confirm that this bahavior is correct (confirm by the designers). In this case, a possbile error in your documentation is present.

    Regards

    Alban