AM335x DDR3 routing

Larbi Joubala

Other Parts Discussed in Thread: AM3358

Hello,

I am building my own six layer pcb based on the am3358. I take as a reference design the beaglebone black.

I have a question about routing ddr3 signals on different layers. I saw that in bbb in a same group for example dq0 the signals are routed on different layers. I dont understand how it works since the signals travel in different speed betwen outer layers and inner layerS. Can someone explain me?

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi,

The difference in speed propagation can be ignored at these trace lengths and frequencies.

0 Larbi Joubala over 10 years ago in reply to Biser Gatchev-XID

Prodigy 220 points

Ok thank you for your answer.

In this case when do I have to take it in account?(frequency, trace length...)

0 Biser Gatchev-XID over 10 years ago in reply to Larbi Joubala

TI__Guru**** 393215 points

What you need to do is follow the DDR3 design guidelines, as given in section 7.7.2.3 from the AM335x Datasheet Rev. J.

0 Biser Gatchev-XID over 10 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

As personal experience I can share, I had to design an AM335x board with DDR3 some time ago. To save time I took a similar approach to yours. I replicated the BBB stackup and copied precisely the DDR3 routing, including GND and power planes. The board didn't even need the software leveling procedure. We copied the BBB DDR3 settings and it's been working for 2 years now (quite a lot of boards produced).

0 Larbi Joubala over 10 years ago in reply to Biser Gatchev-XID

Prodigy 220 points

Thank you for sharing your personal experience.

For me, I prefer building the stackup and the ddr3 routing by myself for training myself and learn. It is my first PCB.

for the stackup, i use :

L1, GND, PWR, L4, GND, L6

instead of in BBB:

L1, GND, L3, L4, PWR, L6

I prefer having GND reference plane for the DDR3 signals.

By the way,

for the ADDR_CTRL group, the maximum skew is it 25 mils or 50 mils?

In the datasheet (Table 7-66) i see

A1 + A2 skew 25mils

AS skew 25 mils.

In BBB, the longest trace in ADDR_CTRL group has 987 mils and the smallest one has 940 mils. It seems to be 50 mils the max skew.

Same question for CLK?

0 Biser Gatchev-XID over 10 years ago in reply to Larbi Joubala

TI__Guru**** 393215 points

Max. skew, if you use the BBB design (without Vtt termination) is 25mils. A2 and AS do not apply in this case. The longest Address/Control trace on BBB is DDR_CKE, which can be excluded from the Address/Control group. All other Address/Control traces are within 9mils, DDR_CLK/CLKn included.

0 Larbi Joubala over 10 years ago in reply to Biser Gatchev-XID

Prodigy 220 points

Ok thank you.

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AM335x DDR3 routing