EDMA3 block move on C6657

Elnur Babishov

Hello!

I try to copy array from DDR3 to L2SRAM using EDMA3 on C6657, but tranfer does not work.

My code:

CSL_Status          status;
CSL_Edma3Handle edma3_handle;
CSL_Edma3Obj        edmaObj;
CSL_InstNum         edmaNum;
CSL_Edma3ChannelObj chObjM;
CSL_Edma3ChannelAttr chAttrM;
CSL_Edma3ChannelHandle      hChannelM = NULL;
CSL_Edma3HwDmaChannelSetup chSetupM;
CSL_Edma3ParamHandle paramHandleM;
CSL_Edma3ParamSetup paramSetupM;

int ChannelNumM = 0;
CSL_Edma3CmdIntr                regionIntr;

    edmaNum = CSL_TPCC_2;

    CSL_edma3Init(NULL);

   edma3_handle = CSL_edma3Open(&edmaObj, edmaNum, NULL, &status);

    chAttrM.regionNum = CSL_EDMA3_REGION_GLOBAL;
   chAttrM.chaNum = ChannelNumM;
   hChannelM = CSL_edma3ChannelOpen(&chObjM, edmaNum, &chAttrM, &status);

    chSetupM.paramNum = 0;
   status = CSL_edma3HwChannelSetupParam(hChannelM, chSetupM.paramNum);

    paramHandleM = CSL_edma3GetParamHandle(hChannelM, chSetupM.paramNum, &status);

    paramSetupM.aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1);
    paramSetupM.cCnt = 1;
    paramSetupM.srcAddr = (Uint32)Mem1;
    paramSetupM.dstAddr = (Uint32)Mem2;
    paramSetupM.linkBcntrld = 0xFFFF;//CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0x0);
    paramSetupM.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, 0);
    paramSetupM.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, 0);
    paramSetupM.option = (1 << 3) ;
    status = CSL_edma3ParamSetup(paramHandleM, &paramSetupM);

    status = CSL_edma3HwChannelControl(hChannelM, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL);

Where is my mistake? All status is Ok.
I do not use L1D cache. I do not use interrupt here.

Thank you.

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

I presume that, you are using CSL initialization procedure for EDMA in your example.

You have CSL based EDMA examples at the below location for C6678 which could be used as sample reference for C6657 as well:

~\ti\mcsdk_2_01_02_06\pdk_C6678_1_1_2_6\packages\ti\csl\example\edma\edma_test.c

The above is the EDMA example test code uses the EDMA CSL functional layer for the c6678 device. You can build it for other targets (C6670, C6657 ) too through copying the above EDMA test source code into a new empty CCS project and link the functional CSL EDMA library (file name : ti.csl.ae66 ) by adding the directory to the library search path to the project properties->File Search Path. Then you can build this EDMA example in CCS and run without any issues.

http://processors.wiki.ti.com/index.php/CSL#Chip_Support_Library_for_C6670

I am also attaching the edma_test.c file here which you could refer as benchmark for C6657 EDMA initialization to validate.

/cfs-file/__key/communityserver-discussions-components-files/791/3312.5807.4162.edma_5F00_test.c

May be, i could recommend few suggestion below:

1. Ensure whether TCINTEN bit is enabled in channel OPT and only then, the interrupt pending register (IPR / IPRH) relevant bit position appropriate to the DMA event would be set on transfer completion

2. Also, please ensure the TCCMODE bit in OPT which would indicate normal or early completion of data transfer. To clarify you that any TCC value cannot be set in the PaRAM and the fact is that the 6-bit TCC would be posted by the TC to the CC after it receives the transfer completion signal from the destination peripheral in normal completion mode. This 6-bit code sets the relevant bit in the interrupt pending register (IPR [TCC] / IPRH [TCC]) for interrupt triggered.

3. I would suggest you to validate the received TCC code in OPT first and obviously, the corresponding bit position in IPR/IPRH would be set which is directly the TCC value and thereafter, the corresponding IER[TCC] / IERH [TCC] bit would be set to generate a EDMA completion interrupt to the DSP

Alternatively, you could also download the latest PROCESSOR-SDK-RTOS-C665x 03_00_00_04 with TI-RTOS support from the below software download link which includes bare metal and TI-RTOS kernel examples demos and it uses chip support libraries, drivers, and basic board-support utilities. May be, you could start with processor SDK getting started guide followed by software development guide as given below:

http://software-dl.ti.com/processor-sdk-rtos/esd/C665x/latest/index_FDS.html

http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Getting_Started_Guide#TI-RTOS_kernel_examples

http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_Software_Developer_Guide

Thanks & regards,

Sivaraj K

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0 Elnur Babishov over 9 years ago in reply to Sivaraj Kuppuraj

Intellectual 895 points

Sivaraj Kuppuraj,

Thank you.
I will study edma_test.c and your suggestions.

Elnur.

0 Elnur Babishov over 9 years ago in reply to Elnur Babishov

Intellectual 895 points

No, I can not understand my mistake.

I slightly modify my code:

CSL_Status status;
CSL_Edma3Handle edma3_handle;
CSL_Edma3Obj edmaObj;
CSL_InstNum edmaNum;
CSL_Edma3ChannelObj chObjM;
CSL_Edma3ChannelAttr chAttrM;
CSL_Edma3ChannelHandle hChannelM = NULL;
CSL_Edma3HwDmaChannelSetup chSetupM;
CSL_Edma3ParamHandle paramHandleM;
CSL_Edma3ParamSetup paramSetupM;

int ChannelNumM = 0;
CSL_Edma3CmdIntr regionIntr;

edmaNum = CSL_TPCC_2;

CSL_edma3Init(NULL);

edma3_handle = CSL_edma3Open(&edmaObj, edmaNum, NULL, &status);

chAttrM.regionNum = CSL_EDMA3_REGION_GLOBAL;
chAttrM.chaNum = ChannelNumM;
hChannelM = CSL_edma3ChannelOpen(&chObjM, edmaNum, &chAttrM, &status);

chSetupM.paramNum = 0;
status = CSL_edma3HwChannelSetupParam(hChannelM, chSetupM.paramNum);

paramHandleM = CSL_edma3GetParamHandle(hChannelM, chSetupM.paramNum, &status);

paramSetupM.aCntbCnt = CSL_EDMA3_CNT_MAKE(64,1);
paramSetupM.cCnt = 1;
paramSetupM.srcAddr = (Uint32)Mem1;
paramSetupM.dstAddr = (Uint32)Mem2;
paramSetupM.linkBcntrld = 0xFFFF;
paramSetupM.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, 0);
paramSetupM.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, 0);
paramSetupM.option = (1 << 3) | (1 << 20);
status = CSL_edma3ParamSetup(paramHandleM, &paramSetupM);

// trigger
status = CSL_edma3HwChannelControl(hChannelM, CSL_EDMA3_CMD_CHANNEL_SET, NULL);

Now, I can see that IPR register set 1 on bit 0, but transfer still does not work. Data of Mem2 != data of Mem1.

TCCMODE bit in OPT is normal complition.
TCC code in OPT is equal 0. I think, It is valid value.

How can I use edma_test. c example on c6657? This example is for c6678.

P.S. In my application, I can successfully run EDMA3 with UART, and it works, but I can not run EDMA3 for copy data in memory.

0 Elnur Babishov over 9 years ago in reply to Elnur Babishov

Intellectual 895 points

It is intresting.
My above code copies data from Mem1 to Mem2 if both buffers (Mem1 and Mem2) are disposed in DDR3 memory. If I place Mem2 in L2SRAM memory, data does not copy from Mem1 to Mem2. Why?

0 Elnur Babishov over 9 years ago in reply to Elnur Babishov

Intellectual 895 points

Hello,

I have some new results in my experiments on data moving with EDMA3.

I have found out that data coping works only with global addressing of memory of CorePac0 (I run data coping on Core0).
So, It works for buffers in DDR3, MSMCSRAM, and L2Sram with addresses: 0x10800000 (L2 CorePack0), 0x11800000 (L2 CorePack1).

If I use 0x800000 for L2SRAM, then data coping does not work.

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EDMA3 block move on C6657