About TDA2xx SOC usb driver

Hi Yue,

Looking at the TDA2x, AM572x, and AM571x TRMs, you can compare the USB base addresses and see that they are all the same for the three devices.

I'm not sure why you modified them. Can you post them here?

If you used the addresses below, and driver still doesn't work, there should be another reason for the malfunction.

USB_WRAPPER1 0x4888 0000

USB_WRAPPER2 0x488C 0000

USB_WRAPPER3 0x4890 0000

USB_WRAPPER4 0x4894 0000

USB_DWC1          0x4889 0000

USB_DWC2          0x488D 0000

USB_DWC3          0x4891 0000

USB_DWC4          0x4895 0000

USB2PHY1           0x4A08 4000

USB2PHY2           0x4A08 5000

Regards,

Stan

hi, Stan

yes, the most of TDA2x and AM572 register addresses are same, I only modified the address as below:

#define DWC_USB_USBLEGSUP (0x880u)
#define DWC_USB_USBLEGCTLSTS (0x884u)
#define DWC_USB_SUPTPRT2_DW0 (0x890u)
#define DWC_USB_SUPTPRT2_DW1 (0x894u)
#define DWC_USB_SUPTPRT2_DW2 (0x898u)
#define DWC_USB_SUPTPRT2_DW3 (0x89Cu)
#define DWC_USB_SUPTPRT3_DW0 (0x8a0u)
#define DWC_USB_SUPTPRT3_DW1 (0x8a4u)
#define DWC_USB_SUPTPRT3_DW2 (0x8a8u)
#define DWC_USB_SUPTPRT3_DW3 (0x8aCu)

and base address I didn't modify

#define USB0_DWC_WRAPPER_BASE_ADDR (0x48880000)
#define USB1_DWC_WRAPPER_BASE_ADDR (0x488C0000)
/****************************************************************************/
//
//dwc base address = USB0_DWC_WRAPPER_BASE_ADDR + USB_DWC_CORE_OFFSET
//
//**************************************************************************/
#define USB_DWC_CORE_OFFSET (0x10000)

#define USB0_USB_PHY_BASE_ADDR (0x4A084000)
#define USB1_USB_PHY_BASE_ADDR (0x4A085000)

I have one question:

what the process of usb transmit-receive data in driver code?
I check the code in AM57x usb driver, only config the register "DWC_USB_DEPCMDPARi " and "DWC_USB_DEPCMD_0 " ,is it OK?

Today I found usb driver can't transmit data, I don't the reason for it?

thanks a lot

Best regards,

Yue

hi, Stan

As we debugged these days, I found some problem of usb transmit. The value of field "HWO" and "BUFSIZ" in TRB always show 1. I think it mean usb controller dma doesn't transmit the data from FIFO. Do you know the reason of it? I check the config of EP/EP0 and TRB, didn't find any problem.

The config of EP0 as below:

/* Set command parameters as 0 initially*/
dEpCmdParm.parm0 = 0;
dEpCmdParm.parm1 = 0;
dEpCmdParm.parm2 = 0;

/* Set the required command parameters */
/* Parm 0 */
HW_SET_FIELD(dEpCmdParm.parm0, DEPCMDPAR_DEPCMDPAR0_DEPCFG_FIFONUM, 0U);
HW_SET_FIELD(dEpCmdParm.parm0, DEPCMDPAR_DEPCMDPAR0_DEPCFG_BRSTSIZ, 0U);
HW_SET_FIELD(dEpCmdParm.parm0, DEPCMDPAR_DEPCMDPAR0_DEPCFG_EPTYPE,
DEPCMDPAR_DEPCMDPAR0_DEPCFG_EPTYPE_CTRL);
HW_SET_FIELD(dEpCmdParm.parm0, DEPCMDPAR_DEPCMDPAR1_DEPCFG_STRMCAP,
DEPCMDPAR_DEPCMDPAR1_DEPCFG_STRMCAP_NOTCAP);

HW_SET_FIELD(dEpCmdParm.parm0, DEPCMDPAR_DEPCMDPAR0_DEPCFG_MPS, 512U);

/* Parm 1 */
HW_SET_FIELD(dEpCmdParm.parm1, DEPCMDPAR_DEPCMDPAR1_DEPCFG_XFERCMPLEN,
DEPCMDPAR_DEPCMDPAR1_DEPCFG_XFERCMPLEN_EN);
HW_SET_FIELD(dEpCmdParm.parm1, DEPCMDPAR_DEPCMDPAR1_DEPCFG_STRMCAP,
DEPCMDPAR_DEPCMDPAR1_DEPCFG_STRMCAP_NOTCAP);

HW_SET_FIELD(dEpCmdParm.parm1, DEPCMDPAR_DEPCMDPAR1_DEPCFG_EPNUMBER, 0U);
HW_SET_FIELD(dEpCmdParm.parm1, DEPCMDPAR_DEPCMDPAR1_DEPCFG_XFERNRDYEN,
DEPCMDPAR_DEPCMDPAR1_DEPCFG_XFERNRDYEN_EN);

HW_SET_FIELD(dEpCmdParm.parm1, DEPCMDPAR_DEPCMDPAR1_DEPCFG_EPDIRECTION,
DEPCMDPAR_DEPCMDPAR1_DEPCFG_EPDIRECTION_OUT);


usbDwcDcdRunDEpCmd(dwc3,
0U,
USB_D_EP_CMD_SETEPCFG,
(usbDwcDcdDEpCmdParms_t *) &dEpCmdParm,
-1,
NULL);


HW_SET_FIELD(dEpCmdParm.parm1, DEPCMDPAR_DEPCMDPAR1_DEPCFG_EPNUMBER, 1U);
HW_SET_FIELD(dEpCmdParm.parm1, DEPCMDPAR_DEPCMDPAR1_DEPCFG_EPDIRECTION,
DEPCMDPAR_DEPCMDPAR1_DEPCFG_EPDIRECTION_IN);

/* Set endpoint configuration for physical endpoint 1 */
usbDwcDcdRunDEpCmd(dwc3,
1U,
USB_D_EP_CMD_SETEPCFG,
(usbDwcDcdDEpCmdParms_t *) &dEpCmdParm,
-1,
NULL);

/* Set Command parameters for Xfer config command */
dEpCmdParm.parm0 = 1;
dEpCmdParm.parm1 = 0;
dEpCmdParm.parm2 = 0;
/* Set endpoint transfer resource configuration for endpoint 0 */
usbDwcDcdRunDEpCmd(dwc3,
0U,
USB_D_EP_CMD_SETEPXFERRESCFG,
(usbDwcDcdDEpCmdParms_t *) &dEpCmdParm,
-1,
NULL);

/* Set endpoint transfer resource configuration for endpoint 1 */
usbDwcDcdRunDEpCmd(dwc3,
1U,
USB_D_EP_CMD_SETEPXFERRESCFG,
(usbDwcDcdDEpCmdParms_t *) &dEpCmdParm,
-1,
NULL);

/* Prepare a buffer for setup packet, initialise a setup TRB and issue
* start transfer command fo rphysical endpoint 0.
*/
/* Set the EP0 state to be in SETUP state */
dwc3->ep0State = USB_DWC_DCD_EP0_STATE_SETUP;
usbDwcDcdRunSetupXfer(dwc3);

/* Enable physical endpoints 0 and 1 and disable all other endpoints */
regVal = 0;
HW_SET_FIELD(regVal, DWC_USB_DALEPENA_USBACTEP0_OUT, 1U);
HW_SET_FIELD(regVal, DWC_USB_DALEPENA_USBACTEP0_IN, 1U);
HW_WR_REG32(dwc3->baseAddr + DWC_USB_DALEPENA, regVal);


/* Set DCTL.runStop = 1 */
HW_WR_FIELD32(dwc3->baseAddr + DWC_USB_DCTL, DWC_USB_DCTL_RUNSTOP,
DWC_USB_DCTL_RUNSTOP_START);

And config of TRB

void usbDwcDcdRunXferSingle(usbDwcDcdDevice_t *dwc3,
uint32_t phEpId,
usbDEpTrb_t *pTrb,
void * pBuf,
uint32_t bufSize,
usbDwcDcdTrbCtrl_t xferType)
{
/* Setup the TRB and issue start transfer command */
pTrb->bufPtrLow = (uint32_t) pBuf;
pTrb->bufPtrHigh = 0;
pTrb->bufSize = bufSize;
pTrb->hwo = TRB_CONTROL_HWO_HW;
pTrb->chn = TRB_CONTROL_CHN_END;
pTrb->lst = TRB_CONTROL_LST_LAST;
pTrb->csp = TRB_CONTROL_CSP_STOP;
pTrb->streamId = 0;
pTrb->trbSts = 0;
pTrb->trbCtrl = xferType;

/* Start the transfer*/
usbDwcDcdStartXfer(dwc3, phEpId, pTrb);
}

void usbDwcDcdStartXfer(usbDwcDcdDevice_t *dwc3,
uint32_t phEpId,
usbDEpTrb_t * pDEpTrb)
{
/* Update the parameters required for the start transfer command */

/* In 32 bit system, the upper 32 bits of the address are set to 0
* In case the system supports more than 32 bits addressing, this
* can be updated with the required address
*/
dEpCmdParm.parm0 = 0;

dEpCmdParm.parm1 = (uint32_t) pDEpTrb;

/* Parameter 2 is unused for this command */
dEpCmdParm.parm2 = 0;
usbDwcDcdRunDEpCmd(dwc3,
phEpId,
USB_D_EP_CMD_STRTXFER,
(usbDwcDcdDEpCmdParms_t *) &dEpCmdParm,
-1,
NULL);
}

void usbDwcDcdRunDEpCmd(usbDwcDcdDevice_t *dwc3,
uint32_t phEpId,
usbDEpCmdType_t pDEpCmdType,
usbDwcDcdDEpCmdParms_t * pDEpCmdParm,
int32_t rscIdx,
uint8_t *pStatus)
{
/* Temporary variables*/
uint32_t dEpCmd = 0U, pollCmdAct = 0U;

/* Set the command type to be issued */
HW_SET_FIELD(dEpCmd, DWC_USB_DEPCMD_0_CMDTYP, pDEpCmdType);

/* Set the resource IDX field if required*/
if(-1 != rscIdx)
{
dEpCmd &= ~(0x1F0000);
dEpCmd |= ((rscIdx << 16U) & 0x1F0000U);
}

/* No interrupt on command completion */
HW_SET_FIELD(dEpCmd, DWC_USB_DEPCMD_0_CMDIOC, DWC_USB_DEPCMD_0_CMDIOC_NO);

/* CmdAct = 1, triggers command execution */
HW_SET_FIELD(dEpCmd, DWC_USB_DEPCMD_0_CMDACT, DWC_USB_DEPCMD_0_CMDACT_ACTIVE);

/* Setup command parameters */
if(pDEpCmdParm != NULL)
{
/* Set param0, param1 and param 2*/
HW_WR_REG32(dwc3->baseAddr + DWC_USB_DEPCMDPAR0_0(phEpId + 1), pDEpCmdParm->parm0);
HW_WR_REG32(dwc3->baseAddr + DWC_USB_DEPCMDPAR1_0(phEpId + 1), pDEpCmdParm->parm1);
HW_WR_REG32(dwc3->baseAddr + DWC_USB_DEPCMDPAR2_0(phEpId + 1), pDEpCmdParm->parm2);
}
/* Issue the command */
HW_WR_REG32(dwc3->baseAddr + DWC_USB_DEPCMD_0(phEpId + 1), dEpCmd);

/* Poll while the command is not complete */
do
{
/* Poll for the cmd Act field in the command register for the
* endpoint for which the command was issued.
*/
//BspOsal_sleep(1);
u_delay(5);
pollCmdAct = HW_RD_FIELD32(dwc3->baseAddr + DWC_USB_DEPCMD_0(phEpId + 1), DWC_USB_DEPCMD_0_CMDACT);
} while(DWC_USB_DEPCMD_0_CMDACT_DONE != pollCmdAct);

/* If output command status pointer is valid */
if(pStatus != NULL)
{
/* Extract status field for command completion */
*pStatus = HW_RD_FIELD32(dwc3->baseAddr + DWC_USB_DEPCMD_0(phEpId + 1), DWC_USB_DEPCMD_0_CMDACT);
}
}


Thank you very much

Best regards,

Yue Zhao

hi, Stan

Yesterday when I debugged , I found the value of field "lst" ,"chn","csp" in TRB all read 1.

As the datesheet's discription:
the value of "lst: read 1 :last TRB in a list,
the value of "chn" read 1:Always 0 in the last TRB of a buffer descriptor.

I don't understand the value of "lst" read 1 mean this TRB is last TRB in the list, but why the value of "chn" also read 1?(As the datesheet's discription . the field of "chnn" must be read 0 in the last TRB)

thank a lot

best regards.

Yue Zhao

Hi Yue,
Sorry for late reply. Unfortunately I don't know the USB driver very well. I can try to look at it.
I've developed the TRM chapter, so I know for sure, there are no hardware difference between AM572x and TDA2x for USB.
Can you meanwhile check if all needed clocks are running for USB?
Regards,
Stan

hi,stan

thank you for your help, I will try to measure the clk of usb module next week.

As my understanding, after I configged the TRB，usb controller dma didn't work,because the value of HWO and BUFSIZ always read 1 when I run it very time.But I am not sure whether I config it correctly?


Do you know who can support this case at TI? We are not familiar with TDA2xx usb. It is very hard to find the solution of this issue for us now.


Thank you very much

best regards,

Yue Zhao

hello, stan,

I config the all clock of usb module as below:

void usbClockCfg(uint32_t portNumber)
{
uint32_t regVal = 0;
uint32_t phyBase = 0;

// enable ocp2scp1
// write this to be able to read/write the PHY registers
HW_WR_REG32(CM_L3INIT_OCP2SCP1_CLKCTRL, 0x1); // AUTO mode
HW_WR_REG32(CM_L3INIT_OCP2SCP3_CLKCTRL, 0x1); // AUTO mode - might not need this

// set OCP2SCP timing
ocp2scp_reset(OCP2SCP1_BASE);
ocp2scp_set_timing(OCP2SCP1_BASE);
// done configurating ocp2scp1

// need this OTG_SS_CLKCLTRL before getting a DPLL_USB lock
regVal = HW_RD_REG32(CM_L3INIT_USB_OTG_SSn_CLKCTRL(portNumber));
regVal |= 0x101U; //OPTFCLKEN_REFCLK960M | MODULEMODE__AUTO
HW_WR_REG32(CM_L3INIT_USB_OTG_SSn_CLKCTRL(portNumber), regVal);

//HW_WR_REG32(CM_L3INIT_CLKSTCTRL, 0x3);
//HW_WR_REG32(CM_COREAON_CLKSTCTRL, 0x3);

// only USB port 0 has USB3.0 PHY which requires a separate DPLL
if (portNumber==0){
USBOTGSS_CLKCONFIG_Vayu_DPLL_USB_OTG_SS(); // USB3 PLL - without PLL, Port never reaches U0
USBOTGSS_USBPHY_PowerSequence_VAYU(portNumber);

}

HW_WR_REG32(CM_AUTOIDLE_DPLL_USB, 1);

// USB 2.0 clocks
// CM_CLKSEL_DPLL_USB.
// DPLL_USB is type B and thus Fclkdcoldo = Fref * M / (N+1) = 960MHz
// Fclkdcoldo is fed to USB (refclk960m)
// {1344, 28-1, 4 }, // 20 MHz
// DPLL_SD_DIV = 4; DPLL_MULT=1344, DPLL_DIV=28. Ref = 20MHz => F=960MHz
// SD_DIV = CEILING ((MUL/(DIV+1))*refClk/250)
HW_WR_REG32(CM_CLKSEL_DPLL_USB, ((4<<24)|(1344<<8)|(27)));
//HW_WR_REG32(CM_CLKSEL_DPLL_USB, 0x0401e009);

// set the CLKOUT_M2??. Value - Fdpll/(2*M2)
HW_WR_REG32(CM_DIV_M2_DPLL_USB, (2<<0)); /* matching linux */

//CM_CLKMODE_DPLL_USB - start the PLL
HW_WR_REG32(CM_CLKMODE_DPLL_USB, 0x7U); // 0x7 is DPLL in LOCK mode

// wait for PLL lock
regVal = HW_RD_REG32(CM_IDLETEST_DPLL_USB);
while((regVal & (1<<0)) != 1){
regVal = HW_RD_REG32(CM_IDLETEST_DPLL_USB);
}

// USB PHY optional 32K clock
HW_WR_REG32(CM_COREAON_USB_PHYn_CORE_CLKCTRL(portNumber), 0x100U);


regVal = *((uint32_t*)(0x4889C110));

HW_SET_FIELD(regVal, DWC_USB_GCTL_CORESOFTRESET, DWC_USB_GCTL_CORESOFTRESET_RESET);
*((uint32_t*)(0x4889C110)) = regVal;

if (portNumber==0){
usb3_phy_reset(portNumber);
}

// turn on the L3INIT_480M_GFCLK bit in the CLKSTCTRL.
// Must have for device mode. Doesn't hurt with host mode
HW_WR_REG32(CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL, 0x100U);


// configuring USB2 PHY registers that are only accessible after clocks
// have been set.
if (portNumber == 0)
{
phyBase = USB0_USB_PHY_BASE_ADDR;
}
else
{
phyBase = USB1_USB_PHY_BASE_ADDR;
}


// USB2.0 only: set USB2PHY_ANA_CONFIG:31 DISCON_DETECT_BYPASS bit
// to fix some possible noise / ringing problems
regVal = HW_RD_REG32(phyBase + USB_USB2PHY_ANA_CONFIG1);
regVal |= (((uint32_t)1<<31)); //DISCON_DETECT_BYPASS
HW_WR_REG32(phyBase + USB_USB2PHY_ANA_CONFIG1, regVal);

}

Did I need to config other clk for the usb?

And I found it has two conditions when the usb transmit wrong.


1)The value of field "lst" ,"chn","csp" in TRB all read 1 and "TRBCTL" read 10
2) The value of "HWO" read 1 and "BUFSIZ" read 8.

BTW, why "TRBCTL" can read 10? I check the TRM , "TRBCTL" should be read "0x0-0x8".

Thanks

Best Regards,

Yue Zhao

HI,stan

Today I found another issue:

When I configged the usb with device mode(write the USB_GCTL[12:13]PRTCAPDIR to 2), but the value of USB_GSTS[0:1] CURMOD always read 0x02(DRD mode not device mode) and I tried to config usb with host mode , have same result.(USB_GSTS[0:1] CURMOD also read 0x02)
.what is reason for it?

Thank you

Yue

Hi. stan,

Thank you very much for your help

one questiuon I don't understand:

It mean than TI's usb core only can work on the DRD mode(OTG mode)?we must use it with DRD mode?
Or we can use it with device mode , we need to program the USB_UTMI_OTG_STATUS register to switch mode?

I think the device mode and DRD mode(OTG mode) is different.

Best regards,

Yue

Hi, stan

BTW, I check the dwc3 usb driver in the linux , have one comment like below:

/**
* WORKAROUND: DWC3 revision < 2.20a have an issue
* which would cause metastability state on Run/Stop
* bit if we try to force the IP to USB2-only mode.
*
* Because of that, we cannot configure the IP to any
* speed other than the SuperSpeed
*
* Refers to:
*
* STAR#9000525659: Clock Domain Crossing on DCTL in
* USB 2.0 Mode
*/
if (dwc->revision < DWC3_REVISION_220A) {
reg |= DWC3_DCFG_SUPERSPEED;
} else {
switch (dwc->maximum_speed) {
case USB_SPEED_LOW:
reg |= DWC3_DSTS_LOWSPEED;
break;
case USB_SPEED_FULL:
reg |= DWC3_DSTS_FULLSPEED1;
break;
case USB_SPEED_HIGH:
reg |= DWC3_DSTS_HIGHSPEED;
break;
case USB_SPEED_SUPER_PLUS:
reg |= DWC3_DSTS_SUPERSPEED_PLUS;
break;
default:
dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
dwc->maximum_speed);
/* fall through */
case USB_SPEED_SUPER:
reg |= DWC3_DCFG_SUPERSPEED;
break;
}
}
dwc3_writel(dwc->regs, DWC3_DCFG, reg);

DWC3 revision 2.2a and earlier have one issue of HW, when it run under SuperSpeed mode.

Does it mean dwc3 only can run with usb3.0 under revision 2.20a ?

BTW, how can I program usb with usb3.0 mode?

Thanks

regards,

Yue

hi,stan

Thank you very much for your patient help first. I know it is a hard problem. But it perplexed us very long time.

let me summarize the problem of this usb driver issue:

We used the TDA2xx usb distance 1 which config with usb2.0 at peripheral mode.

1) Per we debugged ," HWO "bit of TRB always read 1 , it looks like usb controller dma doesn't work, we guessed that event buffer of EndPoint event didn't update every interruption by HW. But I confused that why can event buffer update normally of Device-Specific event?

2) We tried to program usb port to work on usb3.0,but unsucessful. What do we need to do if we want to use it at usb3.0?

3) usb ip core revision in my TDA2xx evm is 2.02a. Can we use it at usb2.0 mode?( according to comments in linux code of dwc3, 2.20a revision and earlier have a issue,it would cause metastability state on Run/Stop bit if we try to force the IP to USB2-only mode)

Hope to get a solution to fix this issue.

Best Regards，

Yue

Also look at USB phy configuration and USB pin mux configuration done correctly.

Regards
Ravi