I need some help understanding the clock input requirements for the 66AK2L06 DSP as stated in the "Hardware Design Guide for Keystone II Devices" (SPRAVB0):
1) PCIECLK: In Table 6, the valid clock frequency is stated as 100MHz, but Table 20 states the three valid clocks as 156.25MHz, 250MHz & 312.5MHz. Which table is correct?
2) SGMIICLK: In Table 6, the valid clock frequency is stated as 125MHz, but Table 15 states the three valid clocks as 156.25MHz, 250MHz & 312.5MHz. Which table is correct?
3) Is CORECLK in table 4 the same as SYSCLK in table 6?
4) SYSCLK: Table 6 states valid input frequencies of 122.88MHz, 153.60MHz and 307.20MHz, but I believe these only apply if the AIF (antenna interface) is used. We're not using AIF, so SYSCLK can be anything between 40MHz & 312.5MHz per table 4, is that correct?
