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DM368 HDVCIP clock

Andreas Gaeer
Intellectual 335 points


Looking at the PERI_CLKCTL reg in the DM368 UBL I see that it is set to a value of 0x243F04FC. According to SPRUFG5a this means ARMCLKS and HDVICPCLKS are running on the same clock source, PLL1CSYSCLK2 that is set to 432 MHz. But according to the specs the HDVCIP should run at max. 340 MHz.

Is this an error in the specs/docs or a bug in the UBL code?

Regards,

 Andreas.

  • 0
    TI__Mastermind 19985 points

    Hi Andreas,

    Bit 26 in PERI_CLKCTL register mentions the clock selection for ARM inside HDVICP. HDVICP comprises of ARM + some hardware co-processors. ARM inside HDVICP runs at 432MHz and the co-processors run at 340MHz, in DM368.

    So the setting of 0x243F04FC is correct in the UBL.

    Regards,

    Anshuman

    PS: Please mark this post as verified, if you think it has answered your question. Thanks

  • 0 in reply to Anshuman Saxena
    Expert 1690 points

    How is this possible?  How does the co-processor know to run at 340MHz?  Aren't the DM365-216, DM365-270, DM365-300, and DM368 processors all the same part just rated for different speeds?  It can't be based off of the ARM clock since the ratio of ARM clock to max HDVICP clock is not the same between variants.

    This suggests otherwise.

    If what you're saying really is true, how would it be possible to underclock a DM365?