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Problems about PLL0 settings of OMAPL138

Other Parts Discussed in Thread: OMAPL138, OMAP-L138

Dear all :

I debug the program on XOMAP chips ( my own boards, not the EVM ), and I re-designed the PCB for the second version, the L138 new chips I got is OMAP. when I debug the new boards, the problem came. it is: when I setup the PLL0 to 300MHz ( DSP side), the ARM report error , pls see the follow:  

Warning: 0x60000060/-1029 @ marker 11103 Error during: Execution, Initialization,  The ICECrusher register scan returned invalid data 

the error comes everytime when I excute :

   // lock pll regs.
   SETBIT(SYSCONFIG->CFGCHIP[0], PLL0_MASTER_LOCK);

in PLL0 setup program.

the XOMAP chip is : XOMAPL138ZWT  $7-95A6PGW  G1

the OMAP chip is: OMAPL13AZWT  $7-9CA9Q9WFR  G1

Now , the OMAPL138 in my new board can only run upto about 150MHz.