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PINMUX options in GLSDK

Jaehee Yun
Prodigy 20 points

How can I determine pinctrl register offset of DRA7x?

ex) dra7-evm.dts

hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
    pinctrl-single,pins = <
        /* this pin is used as a GPIO via mcasp */
        0x2fc   (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
    >;
};

I can not find the value of 0x2fc in TRM.

Best regards.

  • 0
    TI__Mastermind 27950 points
    We have moved your post to the appropriate forum.
  • 0 in reply to Akeem Whitehead
    TI__Mastermind 18940 points
    Hi Jaehee,

    Looks like the register you are looking for is CTRL_CORE_PAD_MCASP2_ACLKR. It is the only place where mcasp8_axr2 is provided and is in mode=1.
    The register is at offset 0x2FC from PADCONFIG registers start (not a real offset provided in TRM, but SW guys' decision) and at offset 0x16FC in Control Module Core. It's address is 0x4A00 36FC.

    Hope this helps.
    Regards,
    Stan
  • 0
    TI__Genius 9905 points
    Hi,

    The pinctrl device tree definition assumes that each address in the child node is relative to the parent address.
    For all the pads, the offset you see is relative to the device tree node dra7_pmx_core (defined in "arch/arm/boot/dts/dra7.dtsi")
    The reg field of this device node indicates the address of 0x4a003400
    Now if you add 0x2fc to this, you'll get 0x4a0026fc - Which confirms the real address of the pinmux register.

    Similarly, you can translate all addresses in this manner
    - Nikhil D