About L1 and L2 in DM6467

Hi Feng,

I have some doubts regarding your question.

1. Do you want to know the basic difference between L1P (Program RAM), L1D (Data RAM) and L2 cache memory ? Then, L1 cache is closer to the core, smaller in size and faster. L1P cache can be configured as direct mapped cache while L1D cache can be mapped as Set associative cache. L2 cache is farther from the core, slower than L1, but of larger size.

2. DO you want to know more about the difference between l1 and L2 cache memory behaviour? Or configuration methodology (direct mapped or set-associative) for L1P and L1D cache memory?

Regards,

Sid

I want to know  the  L2 with different address, but they are all named L2

                        0x0081 8000 to 0x0083 7FFF (128k L2 RAM/Cache)

                        0x1181 7FFF to 0x1183 7FFF  (128k L2 RAM/Cache)

    ---------------------------------------------------------------------------------------------------------

                       L1P with different address, but they are all named L1P

                        0x00E0 8000 to 0x00E0 7FFF (32k L1P RAM/Cache)

                        0x11E0 8000 to 0x11E0 7FFF (32k L1P RAM/Cache)

----------------------------------------------------------------------------------------------------------------

                        L1D with different address, but they are all named L1D

                        0x00F0 8000 to 0x00F0 7FFF (32k L1D RAM/Cache)         

                        0x11F0 8000 to 0x11E0 7FFF (32k L1D RAM/Cache)        

------------------------------------------------------------------------------------------------------------------

Hi Feng,

A line on page 20 of the datasheet says (under the Memory Map) that

These peripherals have their own DMA engine or master port interface to the DMSoC system bus and do not use the EDMA for data
transfers. The "tick mark" symbol indicates that the peripheral has a valid connection through the device switch fabric to the memory region
identified in the EDMA access column.

Here, it can be seen that the second addresses for L1D, L1P and L2 cache are actually C64x+ caches which are actually accessible to peripheral controllers without using DMA for cache transfers. Whereas the first addresses are not directly accessible to all these peripherals unless they use EDMA based transfers. More information may be obtained via DMSoC architecture guide. This may bring about a sharp change in performance of memory cache operations.

Hope this helps.

Regards,

Sid

Hi sid:

Thank you for your answers.

Now, I have got more informaition about the cache.