AM57xx PCIe link problems when using GPIO reset

Other Parts Discussed in Thread: AM5728

Hi,

I'm using a custom AM5728 hardware with a FPGA connected as PCIe endpoint. In the linux device tree, I enabled the the gpio PCIe reset signal for my hardware:

&pcie1 {
    gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>;
};

With this, the link doesn't come up during kernel boot:

[    0.572949] PCI host bridge /ocp/axi@0/pcie@51000000 ranges:
[    0.572960]   No bus range found for /ocp/axi@0/pcie@51000000, using [bus 00-ff]
[    0.572991]    IO 0x20003000..0x20012fff -> 0x00000000
[    0.573017]   MEM 0x20013000..0x2fffffff -> 0x20013000
[    0.603520] dra7-pcie 51000000.pcie: link is not up

The problem is that the maximum link delay in dra7xx_pcie_establish_link() doesn't seem to satisfy the PCIe specification:

    for (retries = 0; retries < 1000; retries++) {
        if (dw_pcie_link_up(pp))
            return 0;
        usleep_range(10, 20);
    }

Link training can take up to 100ms after the reset. After increasing the delay to usleep_range(100, 200), the link comes up successfully.
I hope someone can re-use this information.

Thanks,
Ralf