Other Parts Discussed in Thread: 66AK2H06
Hi,
I designed the 66AK2H06 on my board and have a application as the following. I found it is hard to relate the parameters defined in the csl_edma3.h with that in the Keystone II data sheet. I wonder if you can create an example project for the following use case, don't need to be perfect, with which I can follow and understand the relation of the csl_edma3.h with data sheet. I am using CCS v6.1.3.00033 now.
- Set up timer 0 or 1 for 8KHz interrupt to trigger the EDMA3 (optimized channel?) data transfer from PCIe (or internal share memory, or L2) to share memory inside SOC ( or DDR3A). The 8KHz also output to timer 0 or 1 output pin.
- After above DMA completed, trigger the DSP interrupt to a 8KHz_ISR_service.
- In the end of the above 8KHz_ISR_service, start EDMA3 transfer from internal share memory (or L2) to PCIe, or DDR3A.
- Set up timer 1 or 0 for 100Hz interrupt to start 100Hz_ISR_service.
- Set up error handling interrupt error_ISR_service if possible.
- 8KHz_ISR_service has higher priority than 100Hz_ISR_service.
Thank you very much!