Hi,
I have one question regarding EMIF PHY DLL FCLK of AM5728.
According to the Figure 15-46 of TRM, EMIF_DLL_GCLK is same as EMIF_DLL_FCLK.
Then, according to the table 6-15 of DM, maximum frequency of EMIF_DLL_FCLK is 266MHz(no minimum spec).
However, according to AM572x_ddrz_config.gel, the below comment is written in it.
/* Fields in DDR_PHY_CTRL_1 */
/* Bit[21] - calculated using DataMacro/MDLL clock ratio
* Set to 1 for 532M, so that PHY DLL runs at 266.
* Set to 0 for 400M, so that PHY DLL runs at 400M.
* Ensure PHY DLL lower limit of 266M is not violated.
*/
If DM is correct, maximum frequency of EMIF_DLL_FCLK is 266MHz, This means 400Mhz is over spec. Also if DM is correct, "Ensure PHY DLL lower limit of 266M is not violated" is wrong.
Which is correct? Please advise me.
I appreciate your quick reply.
Best regards,
Michi
