Other Parts Discussed in Thread: TMS320C6746
We are using TI DSP TMS320C6746 in one of our Product.
In that product we are facing issue in HRDY signal generated by the DSP and having below queries. So please look into it and revert asap.
Query 1 :
As per the data sheet when accessing any Read or Write cycle of HPI communication and DSP
is busy then it will generate HRDY (High) signal, Processor need to wait for this cycle till HRDY become Low then complete cycle.
We found that when TI DSP is not access by the processor its chip select is high then also it will generate HRDY signal.
The amplitude of the HRDY signal is 1.5V and duration is around 350us.
In normal cases when actual HRDY is generated with respect to Chip select,At that time voltage level on HRDY is perfect 3.3V.
also duration of the HRDY is very less.
In SPRU578 page number 21 "HRDY pin being driven high only if HCS is active (low). Otherwise HRDY is active (low)
So my query is why such type of signal is generated by DSP. Our system become malfunction due to this.
Provide you feedback regarding it.
