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AM572x DSP1 L2 L2SRAM Definition

Howdy,

I am looking to access the DSP's L2 SRAM in my application. If my understanding is correct, the L2 memory is 288KiB allocated as such:

288 KiB Total

  • 32KiB reserved as SRAM
  • 128KiB allocated as cache
  • 128 KiB allocated as SRAM

The cache allocation is done in my Platform.xdc file, with something like this:

metaonly module Platform inherits xdc.platform.IPlatform
{
  ...
  instance:
  ...
  /*
   *  ======== l2Mode ========
   *  Define the amount of L2 RAM used for L2 Cache.
   *
   *  Check the device documentation for valid values.
   */
  config String l2Mode = "128k";
}

There is an issue, though. When I perform the build it appears that I am only getting access to the allocated 128KiB of SRAM, as opposed to the total 160KiB. This can be seen in the .OUT file, copied below:

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  L2SRAM                00800000   00020000  00001a4a  0001e5b6  RW X

The length of the L2SRAM segment coincides with the 128KiB of SRAM. How do I go about increasing the size of the L2SRAM segment? As far as I can tell, it is not defined anywhere and as such am unable to change it.

Thank you in advance.

  • Hi Caleb,

    I've notified the factory team. They should reply directly here.

    Best Regards,
    Yordan
  • Caleb

    You are right, the total L2 memory can be partition between the L2 Cache and L2 SRAM, so your question is how to configure the cache to be less than 128K

    In the Processor SDK RTOS release the cache is controlled by csl (chip support library) functions that are part of the PDK (Platform Development Kit). Look at the release ->pdk directory->packages->ti->csl  and look at the include file csl_cacheAux.h

    Look at the function

    static inline void CACHE_setL2Size (CACHE_L2Size newSize)

    The values of newSize are defined in the file csl_cache.h at the same location.  And there you can use the function at the start of main to set the L2 cache size. Teh left-over in L2 is SRAM

    Please close the thread if you are happy with this answer

    Ran

  • Howdy,

    Well, actually, what I intend to do is maximize cache to 256k. This should give me the extra 32k of L2 (which is reserved as SRAM). The problem is when i configure the L2Cache mode to 256k. The linker cmd file that is produced is assuming that the total L2 size is 256k instead of the full 288k. This means that when I try to assign the remaining L2 memory as a L2Heap I get an error that the memory section cannot fit in the remainder of the memory segment (which has been set to 0 bytes by XDC)

    But even in the case where I do not want to maximize cache I run into the same error. I set the L2mode to 128k, and after configuro the linker command file only provides a L2SRAM for the remaining 128k of configurable L2 memory, without including the 32k reserved for SDRAM use. Any ideas as to why that 32k of memory is not being in the linker file?

    Thank you.

  • OOPS, I thought I already answer this e2e, so I apologize (I was on vacation last week)

    Well, if part of the memory is not defined, you need to add it. Give it a name like SRAM2 or something and add it to the linker command file - if you use linker command, or add it to the definition of the platform if the project uses RTSC.   Just add another line in the memory definition.

    Does it answer the issue?

    Ran

  • No response for a week.   I close the thread    You can open it again if you are still need