Can you please confirm and provide input on assumption being made below:
The McASP I2S needs to be frequency locked with the tuner sample frequency if we do not want to over or under sample, right? But the tuner IC I'v seen so far does not seem to have this master/slave clock relationship. Since each McASP port need to drive 4 tuners and all 4 tuners and the McASP port need to be frequency locked, right?