C6472 WDOUT not toggling

khaled saab

Hi,

I'm configured timer3 to act as a watchdog and when I inspect the register WDTCR, the WDFLAG is set i.e. However the WDOUT pin is not being asserted low.

Fullscreen WDout.c Download

volatile CSL_TmrRegsOvly  gCSL_WDTmrRegs;	//declare WatchDog timer register

#define WATCHDOG_PERIOD 	1000 //msec
void WatchDogInit(void) {

	gCSL_WDTmrRegs               = (CSL_TmrRegsOvly) CSL_TMR_3_REGS;
	gCSL_WDTmrRegs->EMUMGT_CLKSPD= CSL_TMR_EMUMGT_CLKSPD_RESETVAL;
	gCSL_WDTmrRegs->TIMLO        = CSL_TMR_TIMLO_RESETVAL;
    gCSL_WDTmrRegs->TIMHI        = CSL_TMR_TIMHI_RESETVAL;
    gCSL_WDTmrRegs->PRDLO        = CSL_TMR_PRDLO_RESETVAL;
    gCSL_WDTmrRegs->PRDHI        = CSL_TMR_PRDHI_RESETVAL;
    gCSL_WDTmrRegs->TCR          = CSL_TMR_TCR_RESETVAL;
    gCSL_WDTmrRegs->TGCR         = CSL_TMR_TGCR_RESETVAL;
    gCSL_WDTmrRegs->WDTCR        = CSL_TMR_WDTCR_WDFLAG_MASK;	//clear

	//set the Emulation mode FREE and SOFT (stop immediately)
	gCSL_WDTmrRegs->EMUMGT_CLKSPD &= ~(CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK |
									  CSL_TMR_EMUMGT_CLKSPD_FREE_MASK);

	//set the period
	//convert the WATCHDOG_PERIOD (msec) to timer3 period
	divFactor  = (gCSL_WDTmrRegs->EMUMGT_CLKSPD & CSL_TMR_EMUMGT_CLKSPD_CLKDIV_MASK)
											 >> CSL_TMR_EMUMGT_CLKSPD_CLKDIV_SHIFT;
	gCSL_WDTmrRegs->PRDLO = (WATCHDOG_PERIOD * CLK_countspms())/divFactor;
    gCSL_WDTmrRegs->PRDHI = CSL_TMR_PRDHI_RESETVAL;

	//set to 64 bits watchdog configuration
	gCSL_WDTmrRegs->TGCR  =  ((2  << CSL_TMR_TGCR_TIMMODE_SHIFT   ) |
							  (1  << CSL_TMR_TGCR_TIMHIRS_SHIFT   ) |
							  (1  << CSL_TMR_TGCR_TIMLORS_SHIFT   ));

	//timer is enabled 1 time
	//There is no point in enabling it continuously since the timer will not
	//increment once the timeOut state has been reached.
	gCSL_WDTmrRegs->TCR   =  ((1  << CSL_TMR_TCR_ENAMODE_LO_SHIFT ) |
							  (3  << CSL_TMR_TCR_PWID_LO_SHIFT    ));

	//enable the watchdog
	gCSL_WDTmrRegs->WDTCR =  ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ));

	// Watchdog timer service keys (Reset counters)
    gCSL_WDTmrRegs->WDTCR =  ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ) |
    						  (CSL_TMR_WDTCR_WDKEY_CMD1  << CSL_TMR_WDTCR_WDKEY_SHIFT));
    gCSL_WDTmrRegs->WDTCR =  ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ) |
    						  (CSL_TMR_WDTCR_WDKEY_CMD2  << CSL_TMR_WDTCR_WDKEY_SHIFT));
}

//this is a periodic functions that is called every 100msec
void WatchDogKickPrd(void) {

	gCSL_WDTmrRegs->WDTCR =  ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ) |
							  (CSL_TMR_WDTCR_WDKEY_CMD1  << CSL_TMR_WDTCR_WDKEY_SHIFT));
	gCSL_WDTmrRegs->WDTCR =  ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ) |
							  (CSL_TMR_WDTCR_WDKEY_CMD2  << CSL_TMR_WDTCR_WDKEY_SHIFT));
}


void main(void) {
	WatchDogInit();
}

Did I miss something?

Khaled.

over 10 years ago

0 Rahul Prabhu over 10 years ago

TI__Guru** 116950 points

Khaled,

We will inspect your code and get back to you if we find any issues.

Regards,
Rahul

0 khaled saab over 10 years ago in reply to Rahul Prabhu

Genius 3155 points

Hi Rahul
Any progress with the WDout pin?
Khaled.

0 khaled saab over 10 years ago in reply to khaled saab

Genius 3155 points

Rahul,
I need a response. We are getting closer to releasing the board.
Khaled.

0 Senthilkumar Srinivasan over 10 years ago

TI__Mastermind 43660 points

Khaled,

What is the EVTSTAT value in RSTMUX3 register ? This should be 1 when you configure a timer in watchdog mode and timeout occurs.

Regards,
Senthil

0 khaled saab over 10 years ago in reply to Senthilkumar Srinivasan

Genius 3155 points

Senthil,

configured a global variable to point to #define CSL_DEV_REGS (0x02A80000u) and checked the RSTMUX3.

it starts with a value of 0x00000100 and when the watchdog triggers I get 0x00000110 (see snap shot below).

But I don't see the pulse on WDout pin.

Khaled.

0 Rahul Prabhu over 10 years ago

TI__Guru** 116950 points

Khaleed,

Can you confirm that you have run the timer examples included in the CSL and see the WDOUT occur as expected with the CSL example. I am attaching the source of that examples for your reference.

Fullscreen Timer_example.c Download

/* =============================================================================
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 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
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 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

/** ===========================================================================
 * @file Timer_example.c
 *
 * @path $(CSLPATH)\example\timer\src
 *
 * @desc Example for the usage of General purpose timer CSL APIs
 *
 *  ============================================================================
 *  ============================================================================
 * @n <b> Test Description </b>
 * @n The example illustrates the usage of CSL APIs for using timer.
 * 1. This example configures the first instance of timer
 *    as interrupt or event to be sourced normally by the timer.
 * 2. This enables the timer in one shot mode (for watchdog mode timer is
 *    enabled in continuous mode).
 * 3. The  interrupt handler announces occurrence of each interrupt
 *    to the application.
 * 4. The above said procedure is followed for all the modes of the timer
 *    (i.e. 64 bit timer, dual 32 bit timer( chained and unchained)
 *    and watchdog).
 *
 * =============================================================================
 *      
 *   <b> Procedure to run the example </b>
 *   @verbatim
 *      1. Configure the CCS setup to work with the emulator being used
 *      2. Please refer CCS manual for setup configuration and loading 
 *         proper GEL file
 *      3. Launch CCS window
 *      4. Open project Timer_example.pjt
 *      5. Build the project and load the .out file of the project.
 *          
 *   @endverbatim
 *   
 * =============================================================================
 */ 
/** ============================================================================
 *  Revision History
 *  ===============
 * 07-Jul-2006 TRR Updated for Tomahawk 
 * 29-Jul-2005 PSK updated changes according to revised timer spec. the number
 *                 convention TIM12, TIM34 are changed to TIMLO and TIMHI.
 * 21-Apr-2005 PSK File Created.
 * =============================================================================
 */

#include <csl_tmr.h>
#include <stdio.h>
#include <string.h>
#include <csl_intc.h>
#include <soc.h>
#include <csl_intcAux.h>

/** Handle for the TMR instance */
CSL_TmrHandle         hTmr;

/** change the Instance of the timer and test */
Uint8 IntcInstance = CSL_TMR_0;


/* Locals & Forwards */
void tmrIntcPrdLoLoadDemo(void);
void tmrIntcPrdHiLoadDemo(void);
void tmrIntcChainedDemo(void);
void tmrIntcGptDemo(void);
void tmrWdtModeDemo(void); 

/*
 *****************************************************************************
 *                    INTC related code
 *****************************************************************************
 */

/* Intc Declarations */
CSL_IntcObj                  tmrIntcObj, tmrIntcObj1;
CSL_IntcHandle               tmrIntcHandle, tmrIntcHandle1;
CSL_IntcContext              context, context1;

CSL_IntcEventHandlerRecord   eventHandler[30];
CSL_IntcEventHandlerRecord   record[1];

/* count for ISR */
volatile int intrCnt = 0;

/*
 * ===========================================================================
 * @func   TimerInterruptHandler
 *
 * @desc
 *    Handler for Timer Interrupt
 *
 * @arg    event - interrupt event id
 * ============================================================================
 */
void TimerInterruptHandler (
    CSL_IntcEventId * event
)
{
    intrCnt++;
    CSL_intcEventClear(*event);
}



/** ===========================================================================
 *  @n@b   main
 *
 *  @b Description
 *  @n This is the main function for the file.This initializes the CSL for
 *     INTC, installs interrupt handler for first instance of general purpose
 *     timer and invokes the routine which demonstrates the usage of CSL APis
 *     for General purpose timer
 *
 *  @b Arguments
 *  @verbatim
            None
    @endverbatim
 *
 * <b> Return Value </b>  void
 * ============================================================================
 */
void main (
    void
)
{
    CSL_IntcGlobalEnableState state;

    /* Initialize INTC */
    context.numEvtEntries = 1;
    context.eventhandlerRecord = record;

    CSL_intcInit(&context);

    /*Enable NMIS */
    CSL_intcGlobalNmiEnable();

    /* Enable all interrupts */
    CSL_intcGlobalEnable(&state);

    tmrIntcPrdLoLoadDemo();
    tmrIntcPrdHiLoadDemo();
    tmrIntcChainedDemo();
    tmrIntcGptDemo();
    tmrWdtModeDemo();

    printf(">>>>>> Examples for all the modes of timer are "
    		"completed and PASSED <<<<<<<< \n");
}

/*
 * ===========================================================================
 * @func   tmrIntcPrdLoLoadDemo
 *
 * @desc
 *    This function is example for the Period register loading with value
 *
 * @arg    None
 * ============================================================================
 */
void tmrIntcPrdLoLoadDemo (
    void
)
{
    CSL_TmrObj TmrObj;
    CSL_Status intStat, status;
    CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
    CSL_IntcEventHandlerRecord EventRecord;
    CSL_IntcParam vectId;

    Uint32 LoadValue = 100;

    CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;

    /* Clear local data structures */
    memset(&TmrObj, 0, sizeof(CSL_TmrObj));
    printf("Running Gp Timer Interrupt DUAL UNCHAINED Low....\n");

    /**************************************************************
    * INTC related code      						  *
    **************************************************************/

    /* Open INTC */
    vectId = CSL_INTC_VECTID_12;

    tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_INTC_EVENTID_TINTLO_LOCAL, &vectId,
                                 &intStat);

    /* Bind ISR to Interrupt */
    EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
    EventRecord.arg = (void *)tmrIntcHandle;
    CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);

    /* Event Enable */
    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);

    /**************************************************************/

    /* Initialize GP timer CSL module */
    CSL_tmrInit(NULL);

    hTmr =  CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);

    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Stop the GP Timer */
    status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL);

    /* set the timer mode to unchained dual mode */
    hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED;

    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Load the period register */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void *)&LoadValue);

    /* Start the timer in one shot mode */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, (void *)&TimeCountMode);

    /* INTC related code */
    while (1) {
        if (intrCnt == 1)
	        break;
    }

    /**************************************************************/

    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);

    printf("INTR: The Total number of Events occurred are: 0x%d\n", intrCnt);

    intrCnt = 0;

    /* Stop the GP Timer */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL);

    printf("Example for TIMLO completed\n");

    /* Close the Tmr instance */
    CSL_tmrClose(hTmr);
    CSL_intcClose(tmrIntcHandle);
}

/*
 * =============================================================================
 *   @func   tmrIntcPrdHiLoadDemo
 *
 *   @desc
 *      This function tests the Period register High loading with value
 *
 *   @arg    None
 * =============================================================================
 */
void tmrIntcPrdHiLoadDemo (
    void
)
{
    CSL_TmrObj TmrObj;
    CSL_Status status;
    CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
    CSL_IntcEventHandlerRecord EventRecord;
    CSL_IntcParam vectId;

    Uint32 LoadValue = 100;

    CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;

    /* Clear local data structures */
    memset(&TmrObj, 0, sizeof(CSL_TmrObj));
    printf("\n\n\n\n\nRunning Gp Timer Interrupt DUAL UNCHAINED TIMHI....\n");

    /**************************************************************
    * INTC related code 						  *
    **************************************************************/

    /* Open INTC	*/
    vectId = CSL_INTC_VECTID_13;
    tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_INTC_EVENTID_TINTHI_LOCAL, &vectId,
                                 NULL);

    /* Bind ISR to Interrupt */
    EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
    EventRecord.arg = (void *)tmrIntcHandle;
    CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);

    /* Event Enable */
    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);

    /**************************************************************/

    /* Initialize GP timer CSL module */
    CSL_tmrInit(NULL);
    hTmr =  CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);
    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Stop the GP Timer */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMHI, NULL);

    /* set the timer mode to unchained dual mode */
    hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED;

    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Load the period register */
    status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDHI, (void *)&LoadValue);

    /* Start the timer in one shot mode*/
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMHI, (void *)&TimeCountMode);

    /* INTC related code */
    while (1) {
        if (intrCnt == 1)
	        break;
    }

    /**************************************************************/

    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);

    printf("INTR: The Total number of Events occurred are: 0x%d\n", intrCnt);

    intrCnt = 0;

    /* Stop the GP Timer */
    status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMHI, NULL);
    printf("Example for TIMHI completed\n");

    /* Close the Tmr instance */
    CSL_tmrClose(hTmr);
    CSL_intcClose(tmrIntcHandle);
}

/*
 * ============================================================================
 *   @func   tmrIntcChainedDemo
 *
 *   @desc
 *     This test verifies the Setting of timer to dual 32 bit chained
 *     and one shot mode with INTC
 *
 *   @arg    None
 * ============================================================================
*/
void tmrIntcChainedDemo (
    void
)
{
    CSL_TmrObj TmrObj;
    CSL_Status status;
    CSL_IntcEventHandlerRecord EventRecord;
    CSL_IntcParam vectId;

    Uint32 LoadValue = 100;
    Uint32 LoadValue1 = 0;
    Uint8 preScalValue = 0;

    CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;

    /* set the timer in to one shot mode */
    CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;

    /* Clear local data structures */
    memset(&TmrObj, 0, sizeof(CSL_TmrObj));
    printf("\n\n\n\n\nRunning Gp Timer Interrupt DUAL CHAINED....\n");

    /**************************************************************
    * INTC related code       						  *
    **************************************************************/

    /* Open INTC */
    vectId = CSL_INTC_VECTID_12;
    tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_INTC_EVENTID_TINTLO_LOCAL, \
                                                  &vectId, NULL);

    /* Bind ISR to Interrupt */
    EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
    EventRecord.arg = (void *)tmrIntcHandle;
    CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);

    /* Event Enable */
    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);

    /**************************************************************/

    /* Initialize GP timer CSL module */
    CSL_tmrInit(NULL);

    hTmr =  CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);

    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Reset the GP Timer */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);

    /* set the timer mode to dual chained mode */
    hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_CHAINED;

    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Load the timer high prescale value*/
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PSCHI, (void *)&preScalValue);

    /* Load the period register */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void *)&LoadValue);

    /* Load the period register */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDHI, (void *)&LoadValue1);

    /* Start the timer with one shot*/
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START64, (void *)&TimeCountMode);

	/**************************************************************
    * INTC related code 						  *
    **************************************************************/
    while (1) {
        if (intrCnt == 1)
	        break;
	}
    /**************************************************************/


    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);

    printf("INTR: The Total number of Events occurred are: 0x%d\n", intrCnt);

    intrCnt = 0;

    /* Stop the GP Timer */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);

    printf("Example for timer chained mode\n");

    /* Close the Tmr instance */
    CSL_tmrClose(hTmr);
    CSL_intcClose(tmrIntcHandle);
}

/*
 * =============================================================================
 *   @func   tmrIntcGptDemo
 *
 *   @desc
 *     This test verifies the Setting of timer to GPT mode with INTC
 *
 *   @arg    None
 * =============================================================================
*/
void tmrIntcGptDemo (
    void
)
{
    CSL_TmrObj TmrObj;
    CSL_IntcEventHandlerRecord EventRecord, EventRecord1;
    CSL_IntcParam vectId;
    CSL_Status status;

    CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;

    /* set the timer in to continuous mode */
    CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;

    /* set the timer mode to GPT mode */
    hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_GPT;

    /* load the PRDLO */
    hwSetup.tmrTimerPeriodLo = 0x0f;

    /* load the PRDHI */
    hwSetup.tmrTimerPeriodHi = 0x00;

    /* Clear local data structures */
    memset(&TmrObj, 0, sizeof(CSL_TmrObj));
    printf("\n\n\n\nRunning Gp Timer with INTC....\n");

    /**************************************************************
    * INTC related code            					  *
    **************************************************************/

    /* Open INTC */
    vectId = CSL_INTC_VECTID_12;
    tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_INTC_EVENTID_TINTLO_LOCAL,\
                                                &vectId, NULL);

    vectId = CSL_INTC_VECTID_13;
    tmrIntcHandle1 = CSL_intcOpen(&tmrIntcObj1, CSL_INTC_EVENTID_TINTHI_LOCAL,\
                                                &vectId, NULL);

    /* Bind ISR to Interrupt */
    EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
    EventRecord.arg = (void *)tmrIntcHandle;
    CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);

    EventRecord1.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
    EventRecord1.arg = (void *)tmrIntcHandle1;
    CSL_intcPlugEventHandler(tmrIntcHandle1, &EventRecord1);

    /* Event Enable */
    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);
    CSL_intcHwControl(tmrIntcHandle1, CSL_INTC_CMD_EVTENABLE, NULL);

    /**************************************************************/

    /* Initialize GP timer CSL module */
    CSL_tmrInit(NULL);

    hTmr = CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);

    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Reset the GP Timer */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);

    /* Start the timer with one shot*/
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START64, (void *)&TimeCountMode);

	/**************************************************************
    * INTC related code 						  *
    **************************************************************/
    while (1) {
        if (intrCnt == 1)
	        break;
    }
    /**************************************************************/

    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);

    CSL_intcHwControl(tmrIntcHandle1, CSL_INTC_CMD_EVTDISABLE, NULL);

    printf("INTR: The Total number of Events occurred are: 0x%d\n", intrCnt);

    intrCnt = 0;

    /* Stop the GP Timer */
    CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);

    printf("Example for 64-bit timer mode\n");

    /* Close the Tmr instance */
    CSL_tmrClose(hTmr);
    CSL_intcClose(tmrIntcHandle);
}



/*
 * ============================================================================
 *   @func   tmrWdtModeDemo
 *
 *   @desc
 *     This verifies the Setting of timer to watchdog mode with INTC
 *
 *   @arg    None
 * ============================================================================
 */
void tmrWdtModeDemo (
    void
)
{
    CSL_TmrObj TmrObj;
    CSL_Status status;
    CSL_IntcParam vectId;
    CSL_IntcEventHandlerRecord EventRecord;

    CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;

    /* set the timer in to continuous mode and it is must for watchdog mode */
    CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_CONT;

    CSL_IntcEventId eventId = CSL_INTC_EVENTID_TINTLO_LOCAL;

    Uint16 loadVal = CSL_TMR_WDTCR_WDKEY_CMD1;

    /* set the timer mode to WATCHDOG mode */
    hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_WDT;
    hwSetup.tmrPulseWidthLo = CSL_TMR_PWID_THREECLKS;
    hwSetup.tmrClksrcLo = CSL_TMR_CLKSRC_INTERNAL;
    hwSetup.tmrClksrcHi = CSL_TMR_CLKSRC_INTERNAL;
    hwSetup.tmrClockPulseLo = CSL_TMR_CP_PULSE;
    hwSetup.tmrClockPulseHi = CSL_TMR_CP_PULSE;
    hwSetup.tmrIpGateLo = CSL_TMR_CLOCK_INP_NOGATE;
    hwSetup.tmrIpGateHi = CSL_TMR_CLOCK_INP_NOGATE;

    /* load the PRDLO */
    hwSetup.tmrTimerPeriodLo = 0x100;

    /* load the PRDHI */
    hwSetup.tmrTimerPeriodHi = 0x0;

    /* Clear local data structures */
    memset(&TmrObj, 0, sizeof(CSL_TmrObj));
    printf("\n\n\n\n Running the GP timer in watchdog mode with INTC......\n");

    /**************************************************************
    * INTC related code 						  *
    **************************************************************/

    /* Open INTC */
    vectId = CSL_INTC_VECTID_12;

	if (IntcInstance == 1)
        eventId = eventId + 2;

    tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, eventId, &vectId, NULL);

    /* Bind ISR to Interrupt */
    EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
    EventRecord.arg = (void *)tmrIntcHandle;
    CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);

    /* Event Enable */
    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);

    /**************************************************************/

    /* Initialize GP timer CSL module */
    status = CSL_tmrInit(NULL);

    hTmr =  CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);

    CSL_tmrHwSetup(hTmr, &hwSetup);

    /* Reset the GP Timer */
    status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);

    /* Start the timer in continuous mode*/
    status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_WDT, \
                               (void *)&TimeCountMode);

    status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_WDKEY, \
                               (Uint16 *) &loadVal);

    loadVal = CSL_TMR_WDTCR_WDKEY_CMD2;

    status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_WDKEY, \
                               (Uint16 *)&loadVal);

    /**************************************************************
    * INTC related code and test								  *
    **************************************************************/
    while (1) {
        if (intrCnt == 1)
	        break;
    }

    /**************************************************************/

    CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);

	printf("INTR: The Total number of Events occurred are: 0x%d\n", intrCnt);

    intrCnt = 0;

    /* Close the Tmr instance */
    status = CSL_tmrClose(hTmr);
    CSL_intcClose(tmrIntcHandle);
}

Please refer to the tmrWdtModeDemo function that sets up the timer in watchdog mode.

Regards,

Rahul

0 Rahul Prabhu over 10 years ago in reply to Rahul Prabhu

TI__Guru** 116950 points

Please ensure that you are not setting the timer in one time mode. HEre are the restrictions while using timer in watchdog mode :

Regards,

Rahul

0 khaled saab over 10 years ago in reply to Rahul Prabhu

Genius 3155 points

Rahul,

The code example that you have sent to me is foreign to me, and it will take me time to understand it.

This is said, could the problem be the "One time enabling" (see instruction below, and see the full code above in the first post)?

    //timer is enabled 1 time
   //There is no point in enabling it continuously since the timer will not increment once the timeOut state has been reached.
   gCSL_WDTmrRegs->TCR   = ((1 << CSL_TMR_TCR_ENAMODE_LO_SHIFT ) | (3 << CSL_TMR_TCR_PWID_LO_SHIFT    ));

Khaled.

0 Rahul Prabhu over 10 years ago in reply to khaled saab

TI__Guru** 116950 points

Yes, can you change that to continuous mode and let us know if you see any change.

Also, it may help to determine if you are seeing the same behavior of the EVM as on your board.

Regards,
Rahul

PS: the code that I have provided is part of the CSL examples and using register and functional CSL.

0 khaled saab over 10 years ago in reply to Rahul Prabhu

Genius 3155 points

Rahul,

Made the change but no WDout assertion.

gCSL_WDTmrRegs->TCR = ((2 << CSL_TMR_TCR_ENAMODE_LO_SHIFT ) | (3 << CSL_TMR_TCR_PWID_LO_SHIFT ));

What next?

Khaled.

0 Rahul Prabhu over 10 years ago in reply to khaled saab

TI__Guru** 116950 points

Can you dump the value of the relevant timer registers, especially TCR and TGCR And WDTCR for us to look at.

Regards,
Rahul

0 Raja over 10 years ago in reply to khaled saab

TI__Guru* 81335 points

Can you enable both high and low shift because the watchdog timer can not operate at 32 bit mode?

	gCSL_WDTmrRegs->TCR   =  ((1  << CSL_TMR_TCR_ENAMODE_LO_SHIFT ) |
							  (3  << CSL_TMR_TCR_PWID_LO_SHIFT    ) |
							  (1  << CSL_TMR_TCR_ENAMODE_HI_SHIFT ) |
							  (3  << CSL_TMR_TCR_PWID_HI_SHIFT    ) );

And try below sequence as well,

void WatchDogInit(void) {

	gCSL_WDTmrRegs               = (CSL_TmrRegsOvly) CSL_TMR_3_REGS;
	gCSL_WDTmrRegs->EMUMGT_CLKSPD= CSL_TMR_EMUMGT_CLKSPD_RESETVAL;
	gCSL_WDTmrRegs->TIMLO        = CSL_TMR_TIMLO_RESETVAL;
    gCSL_WDTmrRegs->TIMHI        = CSL_TMR_TIMHI_RESETVAL;
    gCSL_WDTmrRegs->PRDLO        = CSL_TMR_PRDLO_RESETVAL;
    gCSL_WDTmrRegs->PRDHI        = CSL_TMR_PRDHI_RESETVAL;
    gCSL_WDTmrRegs->TCR          = CSL_TMR_TCR_RESETVAL;
    gCSL_WDTmrRegs->TGCR         = CSL_TMR_TGCR_RESETVAL;
    gCSL_WDTmrRegs->WDTCR        = CSL_TMR_WDTCR_WDFLAG_MASK;	//clear

    //set to 64 bits watchdog configuration
	gCSL_WDTmrRegs->TGCR  =  ((2  << CSL_TMR_TGCR_TIMMODE_SHIFT   ) |
								  (1  << CSL_TMR_TGCR_TIMHIRS_SHIFT   ) |
							  (1  << CSL_TMR_TGCR_TIMLORS_SHIFT   ));

    //timer is enabled 1 time
	//There is no point in enabling it continuously since the timer will not
	//increment once the timeOut state has been reached.
	gCSL_WDTmrRegs->TCR   =  ((1  << CSL_TMR_TCR_ENAMODE_LO_SHIFT ) |
							  (3  << CSL_TMR_TCR_PWID_LO_SHIFT    ) |
							  (1  << CSL_TMR_TCR_ENAMODE_HI_SHIFT ) |
							  (3  << CSL_TMR_TCR_PWID_HI_SHIFT    ) );


	//set the Emulation mode FREE and SOFT (stop immediately)
	gCSL_WDTmrRegs->EMUMGT_CLKSPD &= ~(CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK |
									  CSL_TMR_EMUMGT_CLKSPD_FREE_MASK);

	//set the period
	//convert the WATCHDOG_PERIOD (msec) to timer3 period
	divFactor  = (gCSL_WDTmrRegs->EMUMGT_CLKSPD & CSL_TMR_EMUMGT_CLKSPD_CLKDIV_MASK)
											 >> CSL_TMR_EMUMGT_CLKSPD_CLKDIV_SHIFT;
	gCSL_WDTmrRegs->PRDLO = (WATCHDOG_PERIOD * CLK_countspms())/divFactor;
    gCSL_WDTmrRegs->PRDHI = CSL_TMR_PRDHI_RESETVAL;

	//enable the watchdog
	gCSL_WDTmrRegs->WDTCR =  ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ));

	// Watchdog timer service keys (Reset counters)
    gCSL_WDTmrRegs->WDTCR =  ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ) |
    						  (CSL_TMR_WDTCR_WDKEY_CMD1  << CSL_TMR_WDTCR_WDKEY_SHIFT));
    gCSL_WDTmrRegs->WDTCR =  ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ) |
    						  (CSL_TMR_WDTCR_WDKEY_CMD2  << CSL_TMR_WDTCR_WDKEY_SHIFT));
}

0 khaled saab over 10 years ago in reply to Raja

Genius 3155 points

Hi,

Adding the timer Hi did not change the behavior. In all cases, I was under the impress that for 64bits timers, the Hi registers are not used.

Here is the dump of relevent timer registers before and after the watchdog has triggered.

Khaled.

0 Rahul Prabhu over 10 years ago in reply to khaled saab

TI__Guru** 116950 points

From the register dump, it appears that the Enable LO and ENABLE HI field in TCR are being set to 0x3 which is reserved as far as I can tell. The TGCR settings seems ok.

Another key point is the WDEN bit in the WDTCR register is not set. This is the bit that connects watchdog timer output pin to the watchdog
timeout event

Regards,
Rahul

0 khaled saab over 10 years ago in reply to Rahul Prabhu

Genius 3155 points

Rahul,

No error on the TCR = 0x00700070 ==> PWID_LO = 3; ENAMODE_LO = 1 PWID_HI = 3; ENAMODE_HI = 1

On the WDTCR I'm enabling the WDEN bit (see command below).

    gCSL_WDTmrRegs->WDTCR = ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ) |
                              (CSL_TMR_WDTCR_WDKEY_CMD1 << CSL_TMR_WDTCR_WDKEY_SHIFT));
    gCSL_WDTmrRegs->WDTCR = ((CSL_TMR_WDTCR_WDEN_ENABLE << CSL_TMR_WDTCR_WDEN_SHIFT ) |
                              (CSL_TMR_WDTCR_WDKEY_CMD2 << CSL_TMR_WDTCR_WDKEY_SHIFT));

I traced the WDEN bit error to CCS:

If I run the code just after a hardware reset or after a power cycle, I get WDTCR = 0xDA7E4000 (see attached image).

If the watchdog triggers I get WDTC = x0DA7E8000.

If I re-run the code from CCS (Debug Halt, then Debug start), WDTCR = 0xDA&E0000.

But in BOTH cases, If I run the code after a power cycle or if I re-run the code after debug/Restart, I get the SAME behavior i.e. WDout don't toggle.

Khaled.

0 khaled saab over 10 years ago in reply to khaled saab

Genius 3155 points

Rahul,

forgot to attach the WD registers dump if I run the code after a hardware reset or a power cycle.

Khaled.

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C6472 WDOUT not toggling