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DM647 PRST Problem

Thomas9070
Expert 1575 points
Other Parts Discussed in Thread: XIO2001

Hi...

we see a confusing behaviour of the PCI reset pin PRSTn on our custom DM647board. If the PRSTn is asserted (logic 0) we don’t have access to the DSP over JTAG any more. POR and RESET are deassertet (logic 1).

This is contrary to the spruel4b PCI user guide p17:  “The PRST pin is the main PCI hardware reset. This resets most of the PCI logic within the external PCI clock domain. This reset brings PCI-specific registers, sequencers, and signals to a consistent state.” p18: “PRSTz: Entire chip minus on-chip emulation logic is reset”. Also in the DM647 manual (sprs372f) (p84): "...does not reset the test and emulation circuit..."

Practically we see that the entire chip PLUS on-chip emulation logic is reset. Do you have any explanation? Is there a way to connect to DM647 via Jtag with PRST asserted?

bye,

Thomas

  • 0
    TI__Genius 16916 points

    Thomas,

    I agree.  This behavior is not expected.  I'm confirming with the design team about PRST's relationship with the emulation logic.

    Regards,

    Brad

  • 0 in reply to B.C.
    TI__Genius 16916 points

    Thomas,

    Is your emulation session being disconnected when PRSTn is asserted?  If not, then the emulation logic is not being reset.  However, you will not be able to debug the DSP, because the DSP itself is in reset (i.e. you can't read the DSP registers while the DSP is in reset).

    Regards,

    Brad

  • 0 in reply to B.C.
    Expert 1575 points

    Hi Brad,

    ok - so we basically cannot use the Jtag communication when PRST is asserted. In our application we have a XIO2001 PCIe-PCI bridge: PC --> PCIe --> XIO2001 --> PCI --> DM647

    After powerOn, XIO2001 keeps PRST asserted (forever). How is PRST deasserted normally? Does XIO2001 have to be initialized by the PCs BIOS in order to deassert PRST? Or is this job of the PC side driver of XIO2001?

    bye,

    Thomas

  • 0 in reply to Thomas9070
    TI__Genius 16916 points

    Thomas,

    Thanks for the system details.  Unfortunately, I don't have expertise with the XIO2001 bridge.  Looking in the datasheet, I see this information about PRST:

    PCI bus reset: System software has the ability to assert and deassert the PRST terminal on the secondary PCI bus interface. This terminal is the PCI bus reset.  When bit 6 (SRST) in the bridge control register at offset 3Eh (see

     

    Section 4.29) is asserted, the bridge asserts the PRST terminal.  A 0 in the SRST bit deasserts the PRST terminal.

    So it does appear that the PC-side driver has some control over the PRST signal to the DSP.  Please check the register at offset 3Eh to see if SRST is asserted.  If you need further debug help, let me know and I'll move this thread to a XIO2001 related forum.

    Thanks,

    Brad