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Regarding speed of DDR3



Hi;

If we use 2GB DDR3-1833(13-13-13) instead of 2GB DDR3-1600(11-11-11) on same 796.5 Mhz frequency is there any mandatory changes required in U-boot for DM8168 errata 2.1?

In dm8168 based devices, first we used DDR3-1600, and now using DD3-1833, but now device become unstable, is rebooting in 5-15 minutes. 

Note: Frequency is same 796.5 Mhz in both cases, Also pin diagram and other parameters are same for both DDRr.

Regards

Rohit Khatri

  • Hi Rohit,

    Check this DDR3-1833 chip datasheet, make sure it can run at DDR3-1600 mode with 796.5MHz frequency.

    Usually you can run SDRAM devices slower than the max speed as long as you refresh it at a rate which is compliant with the RAM requirements. Running slower than max is not usually an issue. Faster capable devices are OK as long as the memory controller is configured to meet the specific memory's requirements, particularly the refresh frequency.

    You might need new SW leveling, specific for that new DDR3-1833 chips.

    Regards,
    Pavel
  • Thanks for your reply.

    Refresh frequency of older and new DDR is same.
    Also, We have done software leveling with new DDR3, but still same issue is coming.

    Regards
    Rohit Khatri
  • Rohit,

    Is this DDR3-1833 chip JEDEC standard-compliant? Check also that it comply with:
    - Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb and 4Gb (x16-bit only) devices

    Check also if it can run stable at 400MHz.

    Run also u-boot mtest and see if it run fine.

    Regards,
    Pavel
  • Yes, it is JEDEC standard compliant and device is capable of 2GB x16 and x32 bit.

    It is working stable at 675Mhz, but our requirement is 796.5Mhz.

    Also, it is passing all tests under mtest from U-boot.



    Regards

    Rohit Khatri
  • Rohit,

    Rohit Khatri said:
    device is capable of 2GB x16 and x32 bit.

    Do you mean this DDR3-1833 chip is 2GByte/16Gbit capacity? DM816x support up to 512MByte/4Gbit DDR3 chips.

    Rohit Khatri said:
    It is working stable at 675Mhz, but our requirement is 796.5Mhz.

    This is indication of bad (or not enough) SW leveling process. DDR3 require software leveling to tune the device IOs to the timing characteristics of a particular board design. I would suggest more precise SW leveling here.


    Regards,
    Pavel

  • I have another doubt regarding gel file that used for software leveling.

    Main cortex A8 is working at 1200 Mhz, and in gel file it is on 987Mhz, We didn't change this PLL. We changed only timing parameters in gel file for DDR3. (Default 796.5Mhz in gel file, so didn't change)

    So, is it necessary to bring all custom board related change in gel file?

    Also, we iterated leveling 8 times and all time, difference between all were not more than 2 bytes, in many cases all data were same.

    Regards
    Rohit Khatri