Other Parts Discussed in Thread: AM3352
Hi all,
platform sw&hw: linux sdk 6.0;am3352(This cpu can run 1GHz)
We use slave spi in dma mode to receive othe spi master transmission, when cpu runs at 600MHz or 800MHz, the result is ok,
But when cpu runs at 1000MHz and cpu is busy enough, the result is wrong, the data will add 4 16bit word and following right data flow.
For example: 0xXXXX 0xXXXX 0xXXXX 0xXXXX data0 data1 data2 ...
The four repeated 16bit data 0xXXXX is the last data before new dma transmission.
Is there something wrong with dma and bus priority about the 2 bus masters of arm and dma controller when runnig at 1 GHz?
Regards,
Lusheng
