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evm6678 PCIe example receiving data problem

Alexander Bogodarov
Intellectual 900 points

Hello!

I'm trying to run PCIE_evmc6678_wSoCFile_C66BiosExampleProject on my evm6678le board inserted in PC. Program goes in bebug mode to moment of waiting receiving data from RC and receives nothing (I evaluate dstBuf variable, there are all elements null). I have no RC board and that is why I'm writing to 0x70000000 PCIe base address of EP evm6678le board 1 K of data (all words were 0x11111111) by software on PC(PCITree) but I can't see that data recieves in dstBuf variable . Also I've modified Example program on evm6678 and I've scanned range 0x00000000 - 0xFFFFFFFF of internal board adresses for my data (0x11111111) and it shows that there are no such data in board memory. Why can't I receive anything?

Also, can you advise me about scanning function if I've wrote something wrong in it?

unsigned int* t_adr = 0x00000000;

do {

if(*t_adr == 0x11111111){
PCIE_logPrintf (" address = 0x%08x \n", t_adr);
PCIE_logPrintf (" data = 0x%08x \n", *t_adr);
t_adr++;
}else{
t_adr++;
}

} while (true);

  • 0
    TI__Guru**** 161600 points
    Hi Alexander,

    I've notified the support team. They should respond here shortly.

    Could you just specify, which version of the SDK are you using?

    Best Regards,
    Yordan
  • 0
    TI__Guru** 116100 points
    Your C6678 PCIe EP device was enumerated and able to detect by your PC (PCIe RC) ?
    Able to read the configuration registers of EP from your PC ?

    Run the EP program first then try to access it by RP ?
    Actually this PCIe example would do some read/write back and forth, so you may need to modify the code for your requirement.
  • 0 in reply to Yordan Kovachev
    Intellectual 900 points
    I have TI Processor SDK c667x 03.00.00.04,
    CCS 6.1.3., BIOS MCSDK 2.1.2.6, BIOS MCSDK patch01 02.01.02.06.
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 900 points
    Program on PC are able to read all BARs 0 to 5, device ID, etc and able to modify memory of board through BAR1 memspace. But PC didn't modifed base addresses in BARs maybe because of I've programmed board only after PC boot.
  • 0 in reply to Alexander Bogodarov
    TI__Guru* 81335 points
    You can have both Processor SDK and MCSDK installed on your host PC however when developing application we recommend you to use the latest components from Processor SDK for development. Please refer release notes for more information.

    Thank you.
  • 0 in reply to Alexander Bogodarov
    TI__Guru** 116100 points
    Sorry Alexander for delayed responses.
    Check with experts for this issue.
  • 0 in reply to Titusrathinaraj Stalin
    TI__Guru* 95265 points
    I am not familiar with PCI Tree SW. From your description, the PCIE link is up. Who enumerated the PCIE EP? The BIOS of the PC or the PCI Tree SW?

    As you can see the BAR registers of the EP, was the BAR programed by TI RTOS software and unchanged or it was later programed by RC? Can you dump those BAR0 to BAR5 registers and let us know?

    Each BAR corresponding to a memory region in RC. How you know write to 0x7000_0000? Is 0x7000_0000 one of the regions? In the EP, what are the IB translation setting, can you dump out 0x2180_0300 region?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 900 points

    Here is evm6678 in PC hierarchy

    I've programmed board after booting PC and I think BAR0-5 have to stay with no changes after launching PCIe_BIOS_example on it...

    In window below I can write or read any quantity of data through different adresses. I've tryed one adress write transaction and 40 words (dstBuf length in example) and some other quantities of words to write at one click. And while debugging PCIE_example on board in CSS I've examined contents of dstBuf and all adresses in c6678 0x00000000 - 0xffffffff. I've seen that dstBuf had no changes and there was no writen data in board memspace...

  • 0 in reply to lding
    Intellectual 900 points

    Thank you for managing my problem! Here is memdump of 0x2180_0300

  • 0 in reply to Alexander Bogodarov
    TI__Guru* 95265 points
    From your screenshoots,
    - BAR0-5 was programed by DSP program, your RC didn't change it, BAR 1 = 0x7000_0000 looks good
    - In bound translation used IB1, this translation incoming 0x7000_0000 into L2 address 0x1086_C100 address. What you wrote into 0x7000_0000 will be there, you need to looks at 0x1086_c100 region. What are there?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 900 points
    In 0x1086_c100 are all zeros...
  • 0 in reply to lding
    Intellectual 900 points

    It's strange... I can write some adresses with base 0x7000_0000 and then I can read by PCITree program what I've wrote but 0x1086_c100 all zeros... Maybe there are another EP in my PC with 0x7000_0000 base address? Or could it be that for some reason I 've written data in some hidden hardware buffer in PCIe peripheral in evm6678?

  • 0 in reply to Alexander Bogodarov
    TI__Guru* 95265 points
    In the CCS memory window, try to refresh the 0x1086_C100 region to see if data there. Then there is L1DCache, L2Cache check box on memory window, you can check/uncheck to see if data is in the cache or not.

    You can also manual edit the 0x2180_030c from 0x1086_C100 to some other addresses: like MSMC, DDR or other L2 locations in CCS memory window (make sure they are not used by your program). Then, from your PCITree writes some other pattern into 0x7000_0000, then check the new location in CCS memory window to see if you find the pattern. For example, change this register to 0x0c00_0000, then PCITree write some thing, check 0x0c00_0000 for the new pattern.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 900 points

    I've tried to change 0x1086_0000 to 0x0C00_0000 as you described.  Situation does not changed. By viewing memdump in CSS i can't see changes in memory. Also i tried another experiment. After luanching evm6678 I've changed 0x1086_c100 to 0x0c000000, then I wrote some data from PCITree program and then changed back address to 0x1086_C100  and tried to read data by PCITree. I've read by PCITree same data which I've wrote but in theory another data have had to appear in PCITree window. It looks like I'm transacting with another EP device in my PC or I'm loosing something in understanding of PCIe example.

  • 0 in reply to Alexander Bogodarov
    TI__Guru* 95265 points
    Do you have another EP device in the system? If you change the BAR1=0x7000_0000 from CCS to something else (e.g. 0xa000_0000), can your PCI Tree read back BAR1 correctly? If yes, then change 0x2180_030c from 0x7000_0000 to 0xa000_0000, then you write some pattern into 0xa000_0000 from PCI Tree, can you see them in the DSP memory defined by 0x2180_030c register?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 900 points

    I've changed 0x70000000 to 0xa0000000 and wrote data from PCITree to BAR1. From CCS debugger I see no changes in DSP memory

  • 0 in reply to lding
    Intellectual 900 points
    Situation has changed. I've downloaded latest processor sdk for c6678 and ccs6.2.0. Now PCIe example runs and printing message:

    Link is up.
    Checking link speed and # of lanes
    Expect 1 lanes, found 2 lanes (FAIL)
    Expect gen 2 speed, found gen 2 speed (PASS)
    Link width/speed verification FAILed: 8

    What should I do in that case? How can I turn off one link or modify example?

    Also when I've building project an error had occured : Invalid SOC. But building was ended successfully. What doed it mean?
  • 0 in reply to Alexander Bogodarov
    Prodigy 205 points
    Hello, Alexandr!
    I have some succesfull experience in making PCIE connection between PC as RC and EVMC6678 as EP via DMA mechanism. Но все это я делал под Linux) На сколько я понимаю вы сейчас пытаетесь передать данные через PCIE BAR со стороны хост-машины в память DSP. Вы пробовали организовать такую связку или работаете исключительно под Windows ?
  • 0 in reply to Ivan Smolin
    Intellectual 900 points
    Линуксом не влалею к сожалению))) Я работаю под Windows и пробую при помощи специальной программы PCITree записать в BAR1 и увидеть в памяти dstbuf сигнальника что пришло. В такой связке уже получалось записать данные, но в плату xilinc vc707. А с evm6678le запись вроде проходит и считывается обратно программой записанное. Но дебаггером в памяти сигнальника ничего не вижу. Вчера скачал более свежий пример в библиотеках для pcie. Теперь он выводит, что у меня два лэйна, а работать хочет с одним. Такое ощущение, что при включении компьютера в плате загруженная программа по умолчанию в пзу включает два лэйна и чипсет на материнской плате настраивает режим х2.
  • 0 in reply to Alexander Bogodarov
    Prodigy 205 points
    Связку через PCIE с VC707 тоже успешно сделали, но так же работая под Linux-ом. Мне кажется, что новый SDK не самый стабильный в данный момент, поэтому я продолжаю работать с MCSDK версии 2_01_02_06. На счет Windows не знаю и с таким примером на который Вы сослались не работал, но думаю суть проблем для обоих систем одинакова. Под Linux TI дает неплохой пример который лежит вот тут ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie . Фактически там есть кусок драйвера под Linux, проектик для ЦСП и исходники IBL-а. Драйвером производится конфигурация железных блоков ЦСП через BAR-ы, а так же запускается PCIE DMA транзакция и установка прерывания на вход CIC ЦСП. Посмотрите на код, может чем поможет Вам с точки зрения конфигурации PCIE. Если я не ошибаюсь, то и под Linux и под Windows PCIE EP поднимается на стороне ЦСП IBL-ом (если у Вас не новая ревизия камня). Думаю, что возможная проблема у вас именно в нем и Windows как-то криво определяет плату в системе. PCItree на сколько я понимаю представляет из себя некий драйвер под Windows, который запускает транзакцию, но не зная как и куда он кладет данные и через какой BAR что-то более конкретное сказать нельзя.
  • 0 in reply to Ivan Smolin
    Intellectual 900 points
    Иван, спасибо! Посмотрю этот пример. MCSDK я такой же юзаю, а вот processor SDK новый. PCITree, кстати, удобная програмка, там как раз можно именно в нужный BAR и даже в желаемый диапазон адресов записать и можно оттуда же прочитать потом. Мне кажется я уже тут близок к разгадке, попробую еще из биоса режим х1 принудительно задать.
  • 0 in reply to Ivan Smolin
    Intellectual 900 points
    А вы шили в ПЗУ программу для сигнальника? Просто если ее запускать из дебаггера то есть шанс, что настройки платы на шине pcie будут конфликтовать с системными устройствами на материнской плате, а если в постоянную память зашить, то при включении компьютера биос переконфигурирует регистры платы и программа может упасть, у меня так и произошло собственно. Я предполагаю, Вам тоже пришлось хорошо поразбираться с транзакциями поэтому)))
  • 0 in reply to Alexander Bogodarov
    Prodigy 205 points
    В ПЗУ программу шил - вариант загрузки IBL NAND. Но в программе не использовал PCIE, так как к при установке DIP свитчей в соотсветствии с данным вариантом загрузки IBL-ом не происходит конфигурация PCIE. Вероятно Ваша программа падает из-за того что IBL конфигурирует PCIE в режиме POR, т.е. reset сигнал имеет место только при подаче питания на плату. Поэтому просто при перезагрузке host-машины работать не должно.
  • 0 in reply to Alexander Bogodarov
    Intellectual 900 points

    Sorry for another language  talking! Ivan suggested me to explore boot loader example on pcie using linux machine. Also I'm still trying PCIE_evmc6678_wSoCFile_C66BiosExampleProject on Win7. I have FAIL message while running example: expected 1 lane but founded 2 lanes.  Now the question is how to make one link connection.

  • 0 in reply to Alexander Bogodarov
    Intellectual 900 points
    I've modified pcie.h to change speed to Gen1 and inserted code which rewrites PL_LINK_CTRL, LINK_CTRL2, PL_GEN2 regs to configure Gen1 speed and one lane connection and set DIR_SPD to 1. After that PCIe example writes that speed and num of lanes tests are passed in console. Sometimes personal computer can't detect board by PCItree programm after reboot. And my problem stays the same - I can write and read data from computer's side but I can't see anything in dstbuf memory on DSP side.
  • 0 in reply to lding
    Intellectual 900 points
    I've checked cache view in CCS while running pcie example project. I can't see dstbuf in list of cache variables. Is it bad? Can anyone tell me? Maybe I've used wrong platform or configuration or something like that and how to make dstbuf to appear in that list if it needed?
  • 0 in reply to lding
    Intellectual 900 points
    I've checked cache view in CCS while running pcie example project. I can't see dstbuf in list of cache variables. Is it bad? Can anyone tell me? Maybe I've used wrong platform or configuration or something like that and how to make dstbuf to appear in that list if it needed?