Using DM6467T for component SD I/O

George,

Please try the settings below for the THS8200 480i 20bit embedded sync setup. 

Status |= ths8200_rset(0x03,0x11) // chip_ctl           

Status |= ths8200_rset(0x1C,0x03) // dman_cntl   20-bit 4:2:2, use 0x04 for 10-bit bt656       

//bi-level sync setup

Status |= ths8200_rset(0x1D,0x00) // dtg_y_sync1        

Status |= ths8200_rset(0x1E,0x49) // dtg_y_sync2        

Status |= ths8200_rset(0x1F,0x00) // dtg_y_sync3        

Status |= ths8200_rset(0x20,0x00) // dtg_cbcr_sync1     

Status |= ths8200_rset(0x21,0x00) // dtg_cbcr_sync2     

Status |= ths8200_rset(0x22,0x00) // dtg_cbcr_sync3     

Status |= ths8200_rset(0x23,0x22) // dtg_y_sync_upper   

Status |= ths8200_rset(0x24,0x2A) // dtg_cbcr_sync_upper

//horizontal timing

Status |= ths8200_rset(0x25,0x3D) // dtg_spec_a         

Status |= ths8200_rset(0x26,0x14) // dtg_spec_b          

Status |= ths8200_rset(0x27,0x1D) // dtg_spec_c         

Status |= ths8200_rset(0x28,0x7C) // dtg_spec_d         

Status |= ths8200_rset(0x29,0x00) // dtg_spec_d1        

Status |= ths8200_rset(0x2A,0x00) // dtg_spec_e         

Status |= ths8200_rset(0x2B,0x01) // dtg_spec_h_msb     

Status |= ths8200_rset(0x2C,0x6C) // dtg_spec_h_lsb     

Status |= ths8200_rset(0x2D,0x01) // dtg_spec_i_msb     

Status |= ths8200_rset(0x2E,0x8D) // dtg_spec_i_lsb     

Status |= ths8200_rset(0x2F,0x14) // dtg_spec_k_lsb     

Status |= ths8200_rset(0x30,0x00) // dtg_spec_k_msb     

Status |= ths8200_rset(0x31,0x0A) // dtg_spec_k1        

Status |= ths8200_rset(0x32,0xAD) // dtg_speg_g_lsb     

Status |= ths8200_rset(0x33,0x01) // dtg_speg_g_msb     

Status |= ths8200_rset(0x34,0x03) // dtg_total_pixel_msb

Status |= ths8200_rset(0x35,0x5A) // dtg_total_pixel_lsb

Status |= ths8200_rset(0x36,0x00) // dtg_linecnt_msb    

Status |= ths8200_rset(0x37,0x01) // dtg_linecnt_lsb    

Status |= ths8200_rset(0x38,0x84) // dtg_mode   480i        

Status |= ths8200_rset(0x39,0x21) // dtg_frame_field_msb

Status |= ths8200_rset(0x3A,0x0D) // dtg_frame_size_lsb 

Status |= ths8200_rset(0x3B,0x07) // dtg_field_size_lsb 

// CSM - map bt601 code range to DAC full-scale range

Status |= ths8200_rset(0x41,0x40 // csm_clip_gy_low    

Status |= ths8200_rset(0x42,0x40) // csm_clip_bcb_low   

Status |= ths8200_rset(0x43,0x40) // csm_clip_rcr_low   

Status |= ths8200_rset(0x44,0x53) // csm_clip_gy_high   

Status |= ths8200_rset(0x45,0x3F) // csm_clip_bcb_high  

Status |= ths8200_rset(0x46,0x3F) // csm_clip_rcr_high  

Status |= ths8200_rset(0x47,0x40) // csm_shift_gy       

Status |= ths8200_rset(,0x48,0x40) // csm_shift_bcb      

Status |= ths8200_rset(0x49,0x40) // csm_shift_rcr      

Status |= ths8200_rset(0x4A,0xFC) // csm_mult_gy_msb    

Status |= ths8200_rset(0x4B,0x44) // csm_mult_bcb_rcr_msb

Status |= ths8200_rset(0x4C,0xAC) // csm_mult_gy_lsb    

Status |= ths8200_rset(0x4D,0x91) // csm_mult_bcb_lsb   

Status |= ths8200_rset(0x4E,0x91) // csm_mult_rcr_lsb   

Status |= ths8200_rset(0x4F,0xFF) // csm_mode           

//

Status |= ths8200_rset(0x70,0x40) // dtg_hlength_lsb    

Status |= ths8200_rset(0x71,0x03) // dtg_hdly_msb       

Status |= ths8200_rset(0x72,0x59) // dtg_hdly_lsb       

Status |= ths8200_rset(0x73,0x04) // dtg_vlength_lsb    

Status |= ths8200_rset(0x74,0x00) // dtg_vdly_msb       

Status |= ths8200_rset(0x75,0x04) // dtg_vdly_lsb       

Status |= ths8200_rset(0x76,0x04) // dtg_vlength2_lsb   

Status |= ths8200_rset(0x77,0x01) // dtg_vdly2_msb      

Status |= ths8200_rset(0x78,0x0B) // dtg_vdly2_lsb      

Status |= ths8200_rset(0x79,0x00) // dtg_hs_in_dly_msb  

Status |= ths8200_rset(0x7A,0x44) // dtg_hs_in_dly_lsb   adjustment may be required

Status |= ths8200_rset(0x7B,0x00) // dtg_vs_in_dly_msb  

Status |= ths8200_rset(0x7C,0x00) // dtg_vs_in_dly_lsb  

Status |= ths8200_rset(0x82,0x27) // pol_cntl           

Hi,

Thanks for the reply. I did make changes to the THS8200 setting as suggested.

When I run the project, it gets stuck in the code section pasted below (this was happening even before I made the THS8200 settings change),

George,

I am not a software expert, but it looks like this is an input issue not an output issue.

Obviously there is something not generating interrupts when it should.

There is not anything in the ths8200 configuration which can cause this since the ths8200 will blindly receive data without any feedback to the processor.

I will need to defer to a software expert to comment on what could cause the lack of interrupts.

BR,

Steve

Hi,

To provide a background info on this, I tried to run a factory supplied project on the 6467T board and I got the above mentioned problem of getting stuck in the same place waiting for the Frame sync flag.

A TI engineer pointed out that the problem was in I2C setting in BSL file where the following changes were made

    I2C_ICPSC = 337;
    I2C_ICCLKL = 4;
    I2C_ICCLKH = 4;

The original values were

    I2C_ICPSC = 511;
    I2C_ICCLKL = 8;
    I2C_ICCLKH = 8;

I think the above changes were made with respect to 6467 and 6467T and not a problem with the video project. So I'm a little confused where to look for this.

Thanks,

Hi,

Since TVP7002 gives 20 bit output, VPIF channel0 and channel1 should be configured with half of the 10 bit size in the horizontal direction. Please find below updated VPIF settings for SD resolution. Make sure that the VPIF capture is configured with the below settings before VPIF display.

        VPIF_CHCTRL0 = 0            // Capture Parameters
            | ( 0 << 12 )           // Input Field
            | ( 0 << 10 )           // Interlaced Format
            | ( 0 << 9 )            // No Vertical Ancillary
            | ( 0 << 8 )            // No Horizontal Ancillary
            | ( 2 << 6 )            // [2] Interrupt on Bottom Field
            | ( 0 << 4 )            // Raster
            | ( 0 << 3 )            // Y/C on seperate byte streams
            | ( 0 << 1 )
            | ( 0 << 0 );           // Channel Disabled

        VPIF_CHCTRL1 = 0            // Capture Parameters
            | ( 0 << 10 )           // Interlaced Format
            | ( 0 << 9 )            // No Vertical Ancillary
            | ( 0 << 8 )            // No Horizontal Ancillary
            | ( 2 << 6 )            // [2] Interrupt on Bottom Field
            | ( 0 << 4 )            // Raster
            | ( 0 << 3 )            // Y/C on seperate byte streams
            | ( 0 << 1 )
            | ( 0 << 0 );           // Channel Disabled

channel3->regs->IMG_LINE_OFFSET = 720;
channel3->regs->HSIZE_CFG = ( 134 << 16 ) | ( 720 << 0 );
channel3->regs->VSIZE_CFG0 = ( 4 << 16 ) | ( 20 << 0 );
channel3->regs->VSIZE_CFG1 = ( 264 << 16 ) | ( 266 << 0 );
channel3->regs->VSIZE_CFG2 = ( 283 << 16 ) | ( 1 << 0 );
channel3->regs->VSIZE_CFG3 = ( 525 );

channel2->regs->IMG_LINE_OFFSET = 720;
channel2->regs->HSIZE_CFG = ( 134 << 16 ) | ( 720 << 0 );
channel2->regs->VSIZE_CFG0 = ( 4 << 16 ) | ( 20 << 0 );
channel2->regs->VSIZE_CFG1 = ( 264 << 16 ) | ( 266 << 0 );
channel2->regs->VSIZE_CFG2 = ( 283 << 16 ) | ( 1 << 0 );
channel2->regs->VSIZE_CFG3 = ( 525 );

Thanks

Brijesh

Hi All,

Thanks for the replies.

As for the reply from Brijesh, I assume the changes made to the channel2 & channel3 HSIZE_CFG & VSIZE_CFG0, VSIZE_CGF1, VSIZE_CFG2 and VSIZE_CFG3 registers should me made to channel 1 & channel 0 HSIZE_CFG & VSIZE_CFG0, VSIZE_CGF1, VSIZE_CFG2 and VSIZE_CFG3  registers also

8176.tests_video.zip.

I also made similar changes to VPIF_CHCTRL2 and VPIF_CHCTRL3 registers where Y & C are on seperate lines (keeping bit 3 to 0).

After making the above changes the same problem persists.

I'm attaching my project folder as a windows zip file, could someone please verify if the vpif_hd_bt1120.c settings are correct ?

Sincerely,

Hi,

Can you enable error interrupt and see if it is occuring?

Thx,

Brijesh

Hi,

I guess I've to monitor VPIF_INTSTAT register to check for an error interrupt. I tried to breakpoint the code and add VPIF_INTSTAT in the Watch window and I get a message like "Identifier not found - VPIF_INTSTAT".

In order to work around this, I assigned the value of VPIF_INTSTAT to a temporary variable and then displayed the temporary variable

Uint32 temp= 5;

temp = VPIF_INTSTAT; 

temp returns 0 at the breakpoint. which implies there is no error and no frame sync detected. Is this observation correct ?

I'm enabling ERROR_INTERRUPT by,

 VPIF_INTEN    |= VPIF_INTEN_ERROR;  //ERROR enable 
 VPIF_INTENSET |= VPIF_INTEN_ERROR;  //ERROR enable

Sincerely, GV

What is the clock frequency that the PLL should generate for the 20-bit Bt 601, is it 27 MHz  ?

If that is the case, could I reuse the code in CDCE949.c pertaining to setting up PLL for SDTV_480i ?

George,

If you are talking about the TVP7002 clock then it is entirely generated by the TVP and you do not really have any control over it since it is what is called "line locked" which means it will track the incoming video signal.

For 20 bit the clock rate will be nominally 13.5MHz for an NTSC/PAL input video signal.

BR,

Steve

Hi,

In the case of capture, TVP generates pixel clock and provides it to the VPIF. Since there are not interrupts and not even frame sync interrupts, can we check whether TVP is detecting input source correcty?

We can check registers 0x37, 0x38, 0x39, 0x3A in TVP7002 to see if input is SD only. Registesr 0x37 and 0x38 provides detected lines per frame and registers 0x39 and 0x3a provides detected clocks per line. Can you read these registers after configuring TVP7002 for SD mode and see if it is correct?

Thx,

Brijesh

Thanks Brijesh & Steve for responding to the queries.

Instead of trying to do the capture and display at the same time, I'm now just trying to display the colorbars by modifying the video_hd_display_720p.pjt for SDTV_480I. Thus I'm trying to get my display part to work before I try capture. It monitor comes up as "No Output"

I made the changes to _HSIZE_CFG and VSIZE_CFG registers for channel as  was suggested

 channel2->regs->IMG_LINE_OFFSET = 720;
 channel2->regs->HSIZE_CFG = ( 134 << 16 ) | ( 720 << 0 );
 channel2->regs->VSIZE_CFG0 = ( 4 << 16 ) | ( 20 << 0 );
 channel2->regs->VSIZE_CFG1 = ( 264 << 16 ) | ( 266 << 0 );
 channel2->regs->VSIZE_CFG2 = ( 283 << 16 ) | ( 1 << 0 );
 channel2->regs->VSIZE_CFG3 = ( 525 );

 channel3->regs->IMG_LINE_OFFSET = 720;
 channel3->regs->HSIZE_CFG = ( 134 << 16 ) | ( 720 << 0 );
 channel3->regs->VSIZE_CFG0 = ( 4 << 16 ) | ( 20 << 0 );
 channel3->regs->VSIZE_CFG1 = ( 264 << 16 ) | ( 266 << 0 );
 channel3->regs->VSIZE_CFG2 = ( 283 << 16 ) | ( 1 << 0 );
 channel3->regs->VSIZE_CFG3 = ( 525 );

The following is the THS8200 encoder setting,

status |= ths8200_rset(0x03, 0x00);
status |= ths8200_rset(0x38, 0x84);  // 480i  Mode
status |= ths8200_rset(0x82, 0xa0);  // Ignore FID
status |= ths8200_rset(0x1c, 0x03);  // 20-bit YCrCb
status |= ths8200_rset(0x19, 0x03);
status |= ths8200_rset(0x34, 0x03);  // Pixels per line
status |= ths8200_rset(0x35, 0x5a);
status |= ths8200_rset(0x39, 0x21);  // Lines in frame [6..4] = 0x2; Lines in field [2..0]=0x1
status |= ths8200_rset(0x3a, 0x0d);  // Lines in frame 0x20d = 525
status |= ths8200_rset(0x3b, 0x07);  // Lines in field 0x107 = 263 
status |= ths8200_rset(0x7a, 0x44);  // Horizontal offset
status |= ths8200_rset(0x03, 0x00);  // SW reset to reload parameters
status |= ths8200_rset(0x03, 0x01);

The following is the PLL setting for SDTV_480I

            errors |= cdce949_set( 0x13, 0x00 );      // Frequency Select
            errors |= cdce949_set( 0x18, 0x00 );      // Set PLL1_0 Multiplier
            errors |= cdce949_set( 0x19, 0x40 );
            errors |= cdce949_set( 0x1a, 0x02 );
            errors |= cdce949_set( 0x1b, 0x08 );
            errors |= cdce949_set( 0x1c, 0x00 );      // Set PLL1_1 Multiplier
            errors |= cdce949_set( 0x1d, 0x40 );
            errors |= cdce949_set( 0x1e, 0x02 );
            errors |= cdce949_set( 0x1f, 0x08 );
            errors |= cdce949_set( 0x15, 0x02 );      // Output state selection
            errors |= cdce949_set( 0x14, 0xed );      // Switch MUX to PLL1 output
            errors |= cdce949_set( 0x16, 0x01 );      // Set P2DIV Divider
            errors |= cdce949_set( 0x17, 0x01 );      // Set P3DIV Divider
            errors |= cdce949_set( 0x01, 0x00 );      // Select input crystal
            errors |= cdce949_set( 0x05, 0x50 );      // XCSEL - 9 pF
            errors |= cdce949_set( 0x02, 0xb4 );      // Enable PLL
            errors |= cdce949_set( 0x03, 0x01 );      // Set Y1 output divider

In the function, vpif_hd_generate_pattern( Int16 mode ) the hor_incr and ver_incr are 720/8 and 244 respectively.

Can we try to look into the display before I get capture part to work ?

Thanks,

George,

Are you also programming the THS8200 dtg_spec_x registers and sync ampitudes as suggested in a previous post?  The THS8200 will not generate correct sync timing and ampitudes if these are not programmed.

Hi Larry,

I did the change that you had suggested but no effect. Why is that we dont configure the dtg_spec_x registers for the HD formats ?

Thanks,

The memory map and the code foe the VPIF module is also posted below. Is the memory map declared correctly ?

#pragma DATA_SECTION ( bt656NtscYT, ".ddr2_video" );
Uint8 bt656NtscYT[720*244];

#pragma DATA_SECTION ( bt656NtscYB, ".ddr2_video" );
Uint8 bt656NtscYB[720*244];

#pragma DATA_SECTION ( bt656NtscCT, ".ddr2_video" );
Uint8 bt656NtscCT[720*244];

#pragma DATA_SECTION ( bt656NtscCB, ".ddr2_video" );
Uint8 bt656NtscCB[720*244];

if ( mode == MODE_SDTV_480I )
    {
        /* -------------------------------------------------------- *
         *  Setup Display Channel 2 -> Luma[Y]                      *
         * -------------------------------------------------------- */
        channel2->regs->FLD0_Y_STRTADR = ( ( Uint32 )bt1120NtscYT );
        channel2->regs->FLD1_Y_STRTADR = ( ( Uint32 )bt1120NtscYB );

        /* 480I */
        VPIF_CHCTRL2 = 0            // Capture Parameters
            | ( 0 << 12 )           // Input Field
            | ( 0 << 11 )           // Interlaced Format
            | ( 1 << 10 )           // Pixel Data from SDRAM
            | ( 0 << 9 )            // No Vertical Ancillary
            | ( 0 << 8 )            // No Horizontal Ancillary
            | ( 2 << 6 )            // [2] Interrupt on Top & Bottom Field
            | ( 0 << 4 )            // Raster
            | ( 0 << 3 )            // Y/C on seperate byte streams
            | ( 0 << 1 )
            | ( 0 << 0 );           // Channel Disabled

         channel2->regs->IMG_LINE_OFFSET = 720;
         channel2->regs->HSIZE_CFG = ( 134 << 16 ) | ( 720 << 0 );
         channel2->regs->VSIZE_CFG0 = ( 4 << 16 ) | ( 20 << 0 );
         channel2->regs->VSIZE_CFG1 = ( 264 << 16 ) | ( 266 << 0 );
         channel2->regs->VSIZE_CFG2 = ( 283 << 16 ) | ( 1 << 0 );
         channel2->regs->VSIZE_CFG3 = ( 525 );

  /* -------------------------------------------------------- *
  *  Setup Display Channel 3 -> Chroma[CbCr]                 *
  * -------------------------------------------------------- */
        channel3->regs->FLD0_C_STRTADR = ( ( Uint32 )bt1120NtscCT );
        channel3->regs->FLD1_C_STRTADR = ( ( Uint32 )bt1120NtscCB );
        VPIF_CHCTRL3 = 0
            | ( 0 << 12 )           // Input Field
            | ( 0 << 11 )           // Interlaced Format
            | ( 1 << 10 )           // Image data from SDRAM
            | ( 0 << 9 )            // No Vertical Ancillary
            | ( 0 << 8 )            // No Horizontal Ancillary
            | ( 2 << 6 )            // [2] Interrupt on Top & Bottom Field
            | ( 0 << 4 )            // Raster
            | ( 0 << 3 )            // Y/C on seperate byte streams
            | ( 0 << 1 )
            | ( 0 << 0 );           // Channel Disabled

        /* NTSC: 720 x 480 */
      channel3->regs->IMG_LINE_OFFSET = 720;
      channel3->regs->HSIZE_CFG = ( 134 << 16 ) | ( 720 << 0 );
      channel3->regs->VSIZE_CFG0 = ( 4 << 16 ) | ( 20 << 0 );
      channel3->regs->VSIZE_CFG1 = ( 264 << 16 ) | ( 266 << 0 );
      channel3->regs->VSIZE_CFG2 = ( 283 << 16 ) | ( 1 << 0 );
      channel3->regs->VSIZE_CFG3 = ( 525 );
    }

George,

The dtg_spec and sync amplitude registers are typically programmed uniquely for all formats requiring bi-level or tri-level sync insertion.  I am not sure what HD formats you are working with, but the THS8200 defaults appear to be close to those required for 1080i.  You really need to program these registers uniquely for the different sync-on-Y formats.

You may want to look at the THS8200 Y ouput using a scope to see if there is any sign of normal syncs and video on the output.  You can aslo read back the THS8200 dtg2_pixel_cnt and dtg2_line_cnt registers to see if the correct line length and frame length are being decoded from the embedded syncs received.  These should be 858 pixels and 525 lines for 480i60Hz.  The data clock should be 13.5MHz for a 480i 16-bit 4:2:2 interface.

Hi George,

We already have a support for 480i mode in the ths8200 driver. This driver is available at the below link.

http://arago-project.org/git/projects/?p=linux-davinci.git;a=blob;f=drivers/media/video/ths8200.c;h=ad98d98820908bfdd79db5cfe0f52321963f5e93;hb=ac0c0869cd2c06f334657f4192625913c86d24a1

Can you try with this Linux driver?

Thx,

Brijesh

George,

You can download the latest 3.02.00.37 DaVinci PSP release (supports DM6467/DM6467T) in its entirety from here:

http://processors.wiki.ti.com/index.php/DaVinci_PSP_Releases

The settings can be gathered by looking at the video capture driver settings for the TVP7002 decoder and the video display driver settings for the THS8200 encoder.

Regards,

Mark

Hi,

I think I made some progress. From getting no signal output, I'm getting something spurious out even though my aim is to display the color bars.

Quoting from a previous post from Larry Taylor "These should be 858 pixels and 525 lines for 480i60Hz.  The data clock should be 13.5MHz for a 480i 16-bit 4:2:2 interface."

Could you please clarify if this means that Y1 O/P from CDCE949 PLL is 13.5 MHz or 27 MHz since Cb and Cr are sampled at half frequency ?

Thanks,

Hi,

I'm getting the color patterns but they are horizontally skewed and displaying multiple sets instead of one. I'm attaching a pic of what I see.

The clock frequence coming from the PLL is 13.5 MHz and that took care of the problem where the TV monitor didn't show any outputs.

Also I'm attaching VPIF_HD_BT1120.c file, I have made modifications to cater to MODE_SDTV_480i . Could you please go over it and see if there is something wrong standing out with VPIF module.

Any thoughts on this ?

Thanks,

8640.PIx and code.zip

This looks like an incorrect line length setting in the display controller.

If you look closely across the top you can see that the bars are actually correct there.

Is the image stable other than the skew?

Just as a test try changing the line length in small increments up and down to see how the image changes.

Skew like this is always a miss-alignment of line lengths at various places in the processing pipe.

BR,

Steve

Steve beat me to it while I was typing this, it certainly looks like a horizontal width matching problem, where the frame buffer (color bar array) and the display itself  (VPIF configuration) do not appear to agree. In this case it looks like your color bars are slightly too wide (such that they push each subsequent line to the right by ~20 pixels or so) or that your display is slightly too skinny, either way I would do some experimentation as Steve suggests and shorten/widen either the color bar line length or the display line length to see if you can get them aligned.

Hi,

I was able to create a display of the colorbars without any skewing, I had to modify the _CFG registers to the following value (changed from 720),

  channeln->regs->IMG_LINE_OFFSET = 736;
  channeln->regs->HSIZE_CFG = ( 134 << 16 ) | ( 710 << 0 );

Thanks for all the inputs regarding that.

As for getting a proper capture, I'm not getting a proper frame sync interrupt. Quoting from an earlier post, Brijesh Jadav mentioned to check the values of regs 0x37,0x38, 0x39 and 0x3a of TVP7002. The following are the values I have,

Reg 0x37 & 0x38 are read-only and represent "Lines per frame"

reg 0x37 = 0x99; Lines per frame [7....0]
reg 0x38 = 0x02  Lines per frame [11..8]

Lines per frame 0x299 = 655;

Clocks per line  = 0x195 = 405

reg 0x39 = 0x95
reg 0x39 = 0x01

Does the above values look correct for an SD 480i composite input ? Please advice.

Thanks,

Adding to my above post, the HD_CLKIN signal coming out of Pin 28 on TVP7002 is 13.5 MHz.

George,

Your read back does not look correct for 480i.  Line count should be ~525 and clocks/line shoul be ~2716 if using an external 27MHz REFCLK.

Do you have an external 27MHz REFCLK (connected to pin 80 of the TVP7002) ) populated on your board?   If not, make sure the CLK SEL bit in REG 1Ah is set to internal reference.

The 13.5MHz output clock is correct, so the PLL should be set up and seeing an HSYNC.   You may want to check the TVP7002 HSOUT and VSOUT to see if they are at the correct frequencies for 480i (60Hz and 15.374KHz).  If they look OK, then your issue may be related to the TVP7002 embedded sync setup, if you are using those for synchronization.

Are you programming the TVP7002 REGs 40h-49h for embedded sync setup? 

Embedded sync setup should not affect the TVP line count and pixel count readback, however.   Valid readback should depend only on REFCLK operation and HSYNC/VSYNC detection from dicrete input syncs or SOG, which will depend on MUX setup and input signal. 

There may be a part (filter/mux?) between the input connector and TVP7002 that could also be contributing to your problem, if you cannot get a valid line/pixel count read back.

BR,

LArry

Hi,

There is no external clock connected to pin 80 on TVP7002 and reg 1Ah CLK_SEL is configured to select Intercal ref clock which 6.5 MHz.

HSOUT (TP2) on the EVM board actually shows 13.5 kHz.

VSOUT (TP5) on the EVM board shows 60 Hz.

"You may want to check the TVP7002 HSOUT and VSOUT to see if they are at the correct frequencies for 480i (60Hz and 15.374KHz)."  ----> From what you had written above are the values seem interchanged or was it a typo from your side ?

The following is the value for embedded syncs,

    errors |= tvp7002_rset( 0x40, 0x91 );   // AVID Start  145 (118+27)
    errors |= tvp7002_rset( 0x41, 0x00 );   // AVID Start
    errors |= tvp7002_rset( 0x42, 0x0b );   // AVID Stop  11  ((AVID start + 720 + 4) - 858)
    errors |= tvp7002_rset( 0x43, 0x00 );   // AVID Stop

    errors |= tvp7002_rset( 0x44, 0x03 );   // VBLK F0 Offset
    errors |= tvp7002_rset( 0x45, 0x01 );   // VBLK F1 Offse
    errors |= tvp7002_rset( 0x46, 0x13 );   // VBLK F0 Duration
    errors |= tvp7002_rset( 0x47, 0x13 );   // VBLK F1 Duration

Thanks.

George,

Sorry, the values were interchanged.  What are you using for your 480i source?  The HSOUT frequency should be closer to 15.374Khz.

Hi,

I'm using an input from a DVD player as the source. Is that what you meant here?

Yes, the frequency is showing some variation i think, like 15.384 to 15.625. Can that be problematic ? Is it something in the setting of TVP7002 that causes this varation ?

Thanks

Hi,

"Are you programming the TVP7002 REGs 40h-49h for embedded sync setup?"  ---- Are there any recommended values for the embedded sync set-up ?

The input buffer is THS7353 and the settings are assigned for STC low pass filter selection (500 kHz) and low pass filter selection ( 9 MHz). The biasing mode, bits [2..0] is kept as Sync Tip Clamp with low bias for luma and AC bias for chroma.

    Uint8 input_mux  = ( 0 << 5 );  // Input Mux [A];
    Uint8 input_bias_luma   = ( 7 );// Input Mode [Sync Tip Clamp low bias]
    Uint8 input_bias_chroma = ( 4 );// Input Mode [AC Bias Select]

    switch ( mode )
    {
        case MODE_HDTV_1080P:
            stc_lpf = ( 3 << 6 );   // LPF [5 MHz]
            lpf     = ( 3 << 3 );   // LPF [Bypass]
            break;

        case MODE_HDTV_1080I:
        case MODE_HDTV_720P:
            stc_lpf = ( 2 << 6 );   // LPF [5 MHz]
            lpf     = ( 2 << 3 );   // LPF [35 MHz]
            break;

        case MODE_EDTV_576P:
        case MODE_EDTV_480P:
            stc_lpf = ( 1 << 6 );   // LPF [2.5 MHz]
            lpf     = ( 1 << 3 );   // LPF [16 MHz]
            break;

        case MODE_SDTV_576I:
        case MODE_SDTV_480I:
            stc_lpf = ( 0 << 6 );   // LPF [500 kHz]
            lpf     = ( 0 << 3 );   // LPF [9 MHz]
            break;

        default:
            return -1;
    }

    /* ---------------------------------------------------------------- *
     *  Channel 2 - Luma - Green( J2 )                                  *
     * ---------------------------------------------------------------- */
    channel_reg = stc_lpf | input_mux | lpf | input_bias_luma;
    errors |= ths7353_rset( THS7353_CHANNEL_2, channel_reg );

    /* ---------------------------------------------------------------- *
     *  Channel 1 - Chroma - Red( J3 )                                  *
     * ---------------------------------------------------------------- */
    channel_reg = stc_lpf | input_mux | lpf | input_bias_chroma;
    errors |= ths7353_rset( THS7353_CHANNEL_1, channel_reg );

    /* ---------------------------------------------------------------- *
     *  Channel 3 - Chroma - Blue( J1 )                                 *
     * ---------------------------------------------------------------- */
    channel_reg = stc_lpf | input_mux | lpf | input_bias_chroma;
    errors |= ths7353_rset( THS7353_CHANNEL_3, channel_reg );
    return errors;
}

George,

The DVD may have Macrovision copy protection that requires a certain setup in REG 22h and 34h.  Below are TVP7002 settings that we have used here.  
  
01h 35h H-PLL DIV [11:4]
02h A0h H-PLL DIV [3:0]
03h 18h H-PLL Control
04h 80h Phase Select
05h 06h Clamp Start
06h 10h Clamp Width
10h 5Dh SOG / MID-BOT Clamp
11h 40h Sync Separator Thresh
12h 03h Pre-Coast
13h 03h Post-Coast
15h 47h Output Format,4:2:2 Output, Embedded Syncs on
17h 00h Outputs Enabled
18h 01h DATACLK Polarity
19h 00h Input MUX
1Ah 17h CLP/SOG Filter/HS/VS
21h 0Ch HSOUT Start
22h 08h MAC_EN and VS Sel
2Ch 50h ADC Setup
31h 18h ALC Placement
34h 24h MAC Stripper Width based on internal REFCLK frequency
35h 00h VSout Align
3Dh 06h Line Tolerance
3Fh 0Fh Video B/W

I2C REG 480i60 Embedded Sync 

40h 91h AVID Start
41h 00h  
42h 0Bh AVID Stop
43h 00h  
44h 01h F0 V-bit start (# lines before VSYNC)
45h 01h F1 V-bit start (# lines before VSYNC)
46h 26h Length of F0 V-bit interval in lines
47h 26h Length of F1 V-bit interval in lines
48h 02h F0 F-bit position
49h 01h F1 F-bit position

Larry,

Thanks for the input. I tried out the setting that was receommended but still it is waiting on I/O frame sync. I tried with couple of different DVD players and still the same problem happens.

Does it seem like a problem with the set-up in TVP7002 ? Is there any specific registers I need to look closely at ?

As mentioned earlier, in the while loop in the function vpif_hd_display(mode)  is where the program gets stuck.

The code is pasted below

if ( VPIF_INTEN & ( VPIF_INT_CH0 | VPIF_INT_CH1 ) )
    {
        temp = VPIF_INTSTAT;
        while ( ( VPIF_INTSTAT & ( VPIF_INT_CH0 | VPIF_INT_CH1 ) ) == 0 );
        VPIF_INTENCLR = ( VPIF_INT_CH0 | VPIF_INT_CH1 );
    } 

Thanks

Larry,

Adding to the above post, with incorporating the changes to TVP7002 registers, the lines/frame count varies from approx 480 - 680 or so. I got once in my many trials a lines/frame counter of 525. Each time it gives me a different value. Does this ring a bell somewhere ?

Thanks,

George,

Lines/frame should be 525 +/- 1.  This points to an input problem, input MUX setting problem, or sync separator problem. 

Let me double-check the settings I sent using my TVP7002 EVM to make sure we haven't missed something.  I'll get back to you shortly.

Larry

Larry,

I'm not sure if this will add to the confusion but this is an observation that looked interesting.

Just to make sure the registers for TVP7002 held the correct value, I read back all the registers that I configured. Now this causes a little bit of an additional delay because of the read time. When this delay was present I find that the content of regs h37 and h38 is 0x0D and 0x02 respectively which is 525 lines/frame.

I can get this value repetitively all the time when I load and the run the program unlike the case where the value was different every time. Can this be a clue about some input signal timing issues ?

73, George

George,

It will take more than 1 video frame to establish a valid lines/frame count after switching from inactive input to active input. 

In the case where you get erroneous readings, do you program registers before reading lines/frame?  Maybe something is getting programmed that is disrupting the input MUX, or something else.

I did spot something in the 480i embedded sync setup that does not look correct for the V-bit interval.  I'll get back to you on that.  This would not affect lines/frame read back.

Larry

George,

Using the settings, I was able to get a stable picture using the TVP7002EVM directly connected to the THS8200EVM.  The input and SOG MUX settings were configured for my H/W.  Your H/W platform may require different MUX settings.  I would use your original embedded sync settings below.  This was probably tested with the DM6467.

One potential issue may be  having a discrete HSYNC or VSYNC input connected and active when using SOG/Y.  In auto sync detect mode, the TVP will give prioritiy to discrete syncs if both discrete syncs and SOG are active.  You can override auto detection and force to sync separted HSYNC and VSYNC in REG 0Eh.  You can also read sync status in REG 14h to determine which sync source has been automatically selected internally.

    errors |= tvp7002_rset( 0x40, 0x91 );   // AVID Start  145 (118+27)
    errors |= tvp7002_rset( 0x41, 0x00 );   // AVID Start
    errors |= tvp7002_rset( 0x42, 0x0b );   // AVID Stop  11  ((AVID start + 720 + 4) - 858)
    errors |= tvp7002_rset( 0x43, 0x00 );   // AVID Stop

    errors |= tvp7002_rset( 0x44, 0x03 );   // VBLK F0 Offset
    errors |= tvp7002_rset( 0x45, 0x01 );   // VBLK F1 Offset
    errors |= tvp7002_rset( 0x46, 0x13 );   // VBLK F0 Duration
    errors |= tvp7002_rset( 0x47, 0x13 );   // VBLK F1 Duration

Larry

Looking at the datasheet HYSNC_A ( pin 81) , HYSNC_B (pin 82), VYSNC_A ( pin 78), VYSNC_B (pin 79) are grounded.

h0E register is configured as 0x38. The value of reg h14 is 0x6F. Does this look right ?

I think my previous post was a little misleading,

referring to the schematic for the 6467T board showing TVP7002 connection, HYSNC_A ( pin 81) , HYSNC_B (pin 82), VYSNC_A ( pin 78), VYSNC_B (pin 79) are grounded.

Thus h0E register is configured as 0x38 and the value I got from reading h14 is 0x6F which tells that no HSYNC and VYSNC detected on the respective pins but SOG input is detected. Doesn't this look right ?

How do you determine the value of HYSNC O/P width register (06h) ?

Thanks, GV

The sync status looks OK.  If we can conclude that the lines/frame and clocks/line are OK and that we have a 13.5MHz output clock, then it appears we are locked to the input and should focus on DM6467 frame capture using the embedded syncs.

HSYNC output width in REG07h will not influence embedded sync operation.  It's for discrete HSYNC output only.   With most lab pattern generators, it is set to the same width as the 480i SOY sync tip (~64 pixels).

Larry

Hi Larry,

I do get the lines/frame as 525. Clocks/line = 405 using the internal ref clock of 6.5Mhz. The HSOUT is 13.5 to 13.6 kHz.

The DATACLK (pin 28) is 13.5 MHz.

I'm guessing so the TVP7002 is doing its job, is that safe to assume ?

Thanks,

George

George,

The TVP7002 should be be in pretty good shape for 480i60Hz if the conditions below are met.  The internal REFCLK is not a precise clock, so variation in Clocks/line should be expected.  An external 27MHz REFCLK is recommeded for better precision.  It's hard to go beyond this without displaying the output or capturing the output with a logic analyzer.

Lines/frame = ~525

Clocks/line = ~405 (with internal REFCLK)

DATACLK = 13.5MHz

HSOUT = 15.734KHz

VSOUT = 60Hz

Larry

Hi Larry,

The TVP7002 O/P meets the parameters mentioned above.

Just to confirm, HSOUT = 15.734 kHz and not 15.374 kHz which you had mentioned in an earlier post, please confirm ? I'm getting 15.734 kHz exactly.

" It's hard to go beyond this without displaying the output or capturing the output with a logic analyzer." ----> What O/P lines do you want me to probe ?

Is there a way I can use the "Image" (View >> Graph >> Image)  function in TI Code composer to display the input data ?

Thanks,

George

George,

Yes 15.734KHz.  13.5MHz / 858.

Output capture refers to full-frame capture of the GY output port to confirm placement of embedded sync codes.

I am unfamiliar with the View>Graph>Image utility.  Someone familiar with the Code composer environment and frame display capabilites will need to repond to this one.

Regards,

Larry

George Vince said:

Is there a way I can use the "Image" (View >> Graph >> Image)  function in TI Code composer to display the input data ?

Unfortunately the image graph from CCS 3.3 and earlier is not capible of handling interleaved video buffers like I believe you are receiving from the TVP7002 at this point, it only works in planar buffers  (i.e. individual arrays for each color component, Y, Cb, and Cr). You could write a little piece of sorting code to take your image and divide it up into planar buffers which would allow the image graph to work properly as one option.

In newer versions of CCS (CCS v4) there is an image analysis tool that can work with interleaved color data.

Bernie,

Is there a code snippet for converting this that I can use, i don't want to create another level of uncertainity. if it doesn't exist, I can write up an algorithm to create an interlaced video format to convert to Y Cb Cr planar buffers and it would be good if you can review it .

Thanks,

George Vince

The following is the config register setting I have got.

Can you please let me know if this is correct ?  I'm using this same config setting for the display channels 2 & 3.

  channel0->regs->IMG_LINE_OFFSET = 736;
  channel0->regs->HSIZE_CFG = ( 134 << 16 ) | ( 710<< 0 );
  channel0->regs->VSIZE_CFG0 = ( 4 << 16 ) | ( 20 << 0 );
  channel0->regs->VSIZE_CFG1 = ( 264 << 16 ) | ( 266 << 0 );
  channel0->regs->VSIZE_CFG2 = ( 283 << 16 ) | ( 1 << 0 );
  channel0->regs->VSIZE_CFG3 = ( 525 );

Thanks,

Hi,

We already have a utility to convert Semiplanar format to planat format in release package. Please look for convert.c file in examples/others folder.

Thx,

Brijesh

If you don't have the Linux PSP installed to use the utility Brijesh suggests you can do the conversion with a simple, though not necessarily efficient loop:

for (i=0;i<(height*(width/2));i++) //operate over the entire image, processing 2 pixels per loop
{

        crbuf[i] = *outBuf; //pick out a Cr
        outBuf++;
        ybuf[(i*2)] = *outBuf; //pick out first Y
        outBuf++;
        cbbuf[i] = *outBuf; //pick out Cb
        outBuf++;
        ybuf[(i*2)+1] = *outBuf; //pick out second Y
        outBuf++;

}

This should give you the three planar YCbCr 4:2:2 buffers, ybuf, cbbuf, and crbuf, each of which should be arrays of characters.

Bernie,

Thanks for posting the code snippet, I have some questions which can be confusing to type over the forum. Any chance  you would be able to call me, <redacted> ?