Howdy,
I have been searching for information regarding cache misses and memory access in the datasheets/TRM for the AM572x device, but I have been unable to find any performance statistics. I am looking for the miss penalty for data which is sourced from the OCMC3 but is not currently stored in L1 or L2 cache. I did, however, find the following table:
I looks like a L1 miss stalls for at least 9 cycles (to get a read from L2). However, there does not appear to be information regarding the stalled cycles when a L2 miss occurs (to get a read from OCMC3). Do you have these statistics present? Is there a document that I can source this information from?
Thank you in advance!
