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Interfacing TMS320C6416T to ADC0804



I am trying to interface the C6416 DSK with ADC0804. ADC0804 is an 8-bit Analog to Digital Converter and I am reading its 8-bits on the lowest 8 data pins(70-63) of the External Memory Interface (J4). I have grounded the DC_DET of External Peripheral Interface(J3) to enable J3. Till now i am facing a lot of problems in interfacing these.

1. First I want to know how can I set the external memory interface in read and write modes. I thought bit 0 and 1 of CPLD's DC_REG can be used to set the external memory interface in read and write modes but it didn't work as i tried setting and clearing these bits but still some garbage value was written in the CE2 of EMIFA after i had filled 0s in it.

2. Secondly I am using pointers to read and write from the CE2 of EMIFA. So, am i required to select CE2 or is it selected by default, so a conflict between CE0 (SDRAM) and CE2 can be avoided (if any).

  • 1) First try to use pull up/down on the EMIF data pins (instead of connecting ADC0804) just to be sure that you can read something at all.

    Then when you connect ADC0804 you would need to look at the timings and setup the according SETUP, STROBE and HOLD parameters in the EMIF regsiters in order to compatible timings. Basically you will need to compare the timings the ADC0804 datasheet and the EMIF datasheet.

    2) CE0 and CE2 are automayically selected depending on the address range you access. See the memory map described in the C6416T datasheet. To select CE2 you jsut need to access an address that is part of CE2.

  • I tried using EMIF data pins by setting and clearing them (without configuring any of the EMIF registers) and checked there output using a multimeter. This seemed to work fine. Then i interfaced DSK with ADC and set the EMIF CE space control register (CE2CTL) as follows:

    Read Setup   = 0h
    Read Strobe  = 0h
    Read Hold     = 0h

    Write Setup   = Fh
    Write Strobe =  3Fh
    Write Hold    =  3h

    MTYPE = 2h (for 32-bit asynchronous interface)

    and the Global Control Register (GBLCTL) as follows:

    NOHOLD  = 0b

    I did this configuration so that ADC can always write whenever a new output is generated by it at Memory location 0xA0000000, but it didn't work. As soon as i run it the data value at 0xA0000000 changes to 0x00000001 whereas the ADC is giving something else as output and the data value at 0xA0000000 remains same even when ADC changes its output. I tried chaning the CE space control register to

    Read Setup   = Fh
    Read Strobe  = 3Fh
    Read Hold     = 7h

    Write Setup   = 0h
    Write Strobe =  0h
    Write Hold    =  0h

    but still couldn't succeed. Can you please help me out! Here is my code for this program:

     

     

    #include "ledcfg.h"
    #include "dsk6416.h"

    /*
     *  main() - Main code routine, interfaces DC interface with ADC
     */
    unsigned int *EMIFA_Data_Ptr;
    unsigned int *EMIFA_GBLCTL_Ptr;
    unsigned int *EMIFA_CE2CTL_Ptr;
       
    unsigned int Data;


    void main()
    {



        /* Initialize the board support library, must be first BSL call */
        DSK6416_init();
       
        /* EMIFA_CE2_Ptr points to EMIFA Chip enable space 2 */
        EMIFA_Data_Ptr = (unsigned int*)0xA0000000;

        /* EMIFA_GBLCTL_Ptr points to EMIFA Global Control Register */
        EMIFA_GBLCTL_Ptr = (unsigned int*)0x01800000;

        /* EMIFA_GBLCTL_Ptr points to EMIFA Global Control Register */
        EMIFA_CE2CTL_Ptr = (unsigned int*)0x01800010;
       

        while (1)
        {

            *EMIFA_CE2CTL_Ptr = 0xFFF08020;
           
            /* Clearing NOHOLD to enable Hold */
            *EMIFA_GBLCTL_Ptr &= ~(1 << 7);           

            Data = *EMIFA_Data_Ptr;

        }

    }

  • And can you please also tell me what are CPLD (memory mapped at 0x60000000) Daughter Card register's control and status bits for?

  • The CPLD is documented in the Technical Reference that comes with the DSK. Or you can download it from the Spectrum Digital website. They have all the available DSK documentation on their support page for the DSK.

    Sarmad said:
        while (1)
        {

            *EMIFA_CE2CTL_Ptr = 0xFFF08020;
          
            /* Clearing NOHOLD to enable Hold */
            *EMIFA_GBLCTL_Ptr &= ~(1 << 7);          

            Data = *EMIFA_Data_Ptr;

        }

    There is no reason to have the control register writes in this infinite loop. These could cause problems, but I doubt it.

    There is no reason for you to be asserting HOLDn for EMIFA, so NOHOLD has no effect.

    Sarmad said:
    I tried using EMIF data pins by setting and clearing them (without configuring any of the EMIF registers) and checked there output using a multimeter. This seemed to work fine.

    This is not clear what you have confirmed on the EMIF pins. If you have not configured any of the EMIF registers, there should be no valid results. Perhaps some configuration was already done by the GEL file that CCS uses?

    You may be able to learn some things using a multimeter, but get an oscilloscope and look at the pins to see how they are behaving during a read operation. You should see the same bus activity as shown in the datasheet and EMIF User's Guide for asynchronous reads. When CE2 is low, you should see the data values from the ADC.