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SRIO producer and consumer packets flow

Taras Kolesko
Expert 1730 points

Hello again.

I'm working with SRIO_tput_benchmarking project. When i launch it, the system says

"WARNING: Please ensure that the CONSUMER is executing before running the PRODUCER!!"


I wonder, if that really matters, in which order should producer and consumer starts? Because  F.E., my board has DSP and FPGA, i launch it in board-to-board 4 port 1x line, and FPGA (producer) starts earlier than consumber by default. I will not be able to track and receive packets from FPGA?

  • 0
    TI__Guru** 116980 points
    Taras,

    Please refer to the documentation of the SRIO benchmark project as specified here:
    processors.wiki.ti.com/.../Processor_SDK_RTOS_SRIO

    Let us know if this doesn`t suffice and you still have any questions regarding the same.

    Regards,
    Rahul
  • 0
    TI__Guru** 116100 points
    Try to connect two cores (core 0 and core1) and run the code.

    Refer to the below log from C6670 EVM:

    [C66xx_0] ********************************
    *********** CONSUMER ***********
    ********************************
    WARNING: Please ensure that the CONSUMER is executing before running the PRODUCER!!
    Debug: Waiting for module reset...
    Debug: Waiting for module local reset...
    Debug: Waiting for SRIO ports to be operational...
    Debug: SRIO port 0 is operational.
    Debug: Lanes status shows lanes formed as one 4x port
    Debug: AppConfig Tx Queue: 0x2a0 Flow Id: 0
    Debug: SRIO Driver Instance 0x@008619a0 has been created
    Debug: Running test in polled mode.
    Debug: SRIO Driver handle 0x8619a0.


    [C66xx_1] ********************************
    *********** PRODUCER ***********
    ********************************
    WARNING: Please ensure that the CONSUMER is executing before running the PRODUCER!!
    Debug(Core 1): Waiting for SRIO to be initialized.
    Debug: AppConfig Tx Queue: 0x2a1 Flow Id: 1
    Debug: SRIO Driver Instance 0x@008618b0 has been created
    Debug: Running test in polled mode.
    Debug: SRIO Driver handle 0x8618b0.


    Latency: (DIO_NW, 5.000GBaud, 4X, tab delimited)
    Core Lanes Speed Conn MsgType PktSize NumPkts MnLCycs AgLCycs MxLCycs
    1 4 5.000 C-I-C DIO_NW 4 100 704 705 755
    1 4 5.000 C-I-C DIO_NW 8 100 704 704 719
    1 4 5.000 C-I-C DIO_NW 16 100 701 719 734
    1 4 5.000 C-I-C DIO_NW 32 100 740 746 758
    1 4 5.000 C-I-C DIO_NW 64 100 794 811 827
    1 4 5.000 C-I-C DIO_NW 128 100 920 934 940
    1 4 5.000 C-I-C DIO_NW 256 100 1154 1171 1174
    1 4 5.000 C-I-C DIO_NW 512 100 1316 1325 1337
    1 4 5.000 C-I-C DIO_NW 1024 100 1622 1622 1642
    1 4 5.000 C-I-C DIO_NW 2048 100 2216 2219 2236
    1 4 5.000 C-I-C DIO_NW 4096 100 3404 3416 3424
    1 4 5.000 C-I-C DIO_NW 8192 100 5798 5803 5818

    [C66xx_0] Throughput: (RX side, DIO_NW, 5.000GBaud, 4X, tab delimited)
    Core Lanes Speed Conn MsgType OHBytes PktSize Pacing Thruput PktsSec. NumPkts PktLoss AgPCycs AgLCycs AgICycs AgOCycs Seconds
    0 4 5.000 C-I-C DIO_NW 16 4 0 83.99 2624672.00 12600000 No 381 21 360 0 4.80
    0 4 5.000 C-I-C DIO_NW 16 8 0 167.98 2624672.00 12600000 No 381 21 360 0 4.80
    0 4 5.000 C-I-C DIO_NW 16 16 0 335.96 2624672.00 12600000 No 381 21 360 0 4.80
    0 4 5.000 C-I-C DIO_NW 16 32 0 671.92 2624672.00 12600000 No 381 21 360 0 4.80
    0 4 5.000 C-I-C DIO_NW 16 64 0 1343.83 2624672.00 12600000 No 381 21 360 0 4.80
  • 0 in reply to Titusrathinaraj Stalin
    Expert 1730 points
    I understand (at least a little) a process on core to core execution. But in my case i'm trying to catch data from FPGA (producer), which starts to send data through SRIO much earlier than consumer. For some reason i can't see data, nor in socket variables neither in memory map. I'm sure that FPGA is sending packets, and i wonder, is it that FPGA (producer) starts before, can be an issue?