Hi I am experiencing an issue. The RGMII interface is not working as expected and after further review we discovered that we did not have PCB delays as required to meet the setup/hold requirements on the RGMII clock. As per the Sitara documentation and errata an internal delay is not supported in the Sitara. Currently we are noticing that the RGMII CLK from the Sitara is at 25MHz instead of 125MHz as expected. We have reviewed their register settings etc and are unable to determine the reason for the clock frequency, any help would be appreciated.
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