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DM385 DDR3/DDR3L memory configuration support

Other Parts Discussed in Thread: DM385, DM388

A customer wants to understand if the following configuration is supported by the DDR memory controller on the DM385.

The customer wants to support 1GB and 2GB options with DDR3 and DDR3LP.  They would really like to do this with one memory device, but want to understand the configuration(s) supported to enable both 1GB and 2GB options.

  • Hello,

    Reviewing the technical documents for DM38x

       a) errata - 2.1.2 special requirements for PLL_DDR for even M2 Post Divider

                          3.1.3 customers have to follow the DDR3 layout guidelines, and then fillout the Seed DDR3 out clock polarity and DQS levelling spreadsheet.

       b) datasheet - 32bit DDR3, DDR3L implementation (normally 32bit is 2 x16bit devices), 400 - 533Mhz DDRclk, 800-1066 operation

                          6.2 - DDR3 1.5v, DDR3L 1.35v

                          8.1.3 - suggests that memory device capacity is 128 to 4Gbyte

       c) technical reference manual

                           section 7.2 sizing, RSIZE number of rows, PAGESIZE number of columns, IBANK, EBANK number of chip selects, 15bit address bus (A14.0)

                           so supporting two devices we can have 2DDR3 with 2 chip selects and 16bit width, 

                           so supporting two devices we can have 2DDR3 with 1 chip selects and 32bit width, (more memory bandwidth 32bit access)

    The customer can have a 1Gbyte x 16, 2Gbyte x 16, 1Gbyte x (2x16), 2Gbyte x (2x16), depending on the memory bandwidth needs for their application.   

    Regards,

    Joe Quintal

                           

  • Joe,
    Thank you for the response. I do want to clarify one item regarding the statements in the Technical Reference Manual about chip selects. The response above suggests that 2 chip selects are available. However, the DM385 datasheet only has one chip select on the DDR interface brought out. I suspect this may be a nuance between the technical reference manual describing what the IP block can do and the data sheet which indicates what a specific device can support.

    Would you please clarify this point? If my thinking is correct, then what are the supportable configurations?
  • Hi Joe,

    Thanks for the help.  Here are more questions from the customer:

    8.13 in the data sheet

    Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb devices

     

    These say bit not byte. 4Gb is only 500MB. Is he saying the Datasheet is wrong?

     

    I guess what I really need to know is what is the largest Gbit of RAM I can use and can I just use 1 chip.

     

    If I can just use one do I just leave the other 16 address lines open?

  • The DM385 DDR3 interface has a 32 bit data bus with a single chip select. Since DDR3 memory devices do not come in x32 configurations, you're choices are to use either use x16 or x8 memory devices. This is by definition in the JDEC spec.

    The maximum DDR3 address space supported on the DM385 is 1GByte (8GBit). This means no matter what memory device configuration you use, we can only address up to 1GByte. That's the max total DDR3 we can have on the DM385.

    The ideal configuration is to use two x16 memory devices, one on each half of the 32-bit data bus. This would give you maximum bandwidth because you would be moving 32 bits of data at a time. So for maximum bandwidth, you would use two x16 4Gbit memory devices for a total of 8Gbit of storage with 32 bits of data.

    If you only want to use one memory device, I assume for either space savings or power savings, then you could use a single x16 8Gbit memory device. This would still give you the full 1GByte of memory storage. The disadvantage is that you now only have a 16-bit data bus so only half the bandwidth compared to if you were to use all 32 bits using two memory devices.

    If you end up only using a single x16 memory device, which is okay to do, then you can leave the other 16 data lines (upper half of the data bus) unconnected. Then in software you would enable to internal pull-down resistors on those unused IO lines to keep them from floating wildly.

    What is the reason for only wanting a single memory device? I ask because the use cases I typically see have the whole data bus populated with memory devices. Just saying it's not as common to only use half the bus.

  • Hello Brad,

    Adam is getting this info for me. I am going to be using the DM385 on my new project.

    You say the DM385 can only have 1GB of DDR3 RAM but page 1 of the Data sheet says it can have a total of 2GB:

    – Up to Two x 16 Devices, 2GB of Total
    Address Space

    Is the data sheet correct?

    I am running very low on PCB space and that is why I would prefer to have only one DDR3 chip. 1GB of RAM is going to be cutting it close so I may need to do 2GB. If I could do 2GB with one chip I would prefer that. If I need to do two 1GB chips then I will start with 1 chip, run tests and possibly add the other 1GB if needed. I just need confirmation that this can be done because the data sheet is not very clear in this area.

    Thank you,
  • Brian,

    So I will admit I made an educated assumption. I agree with you that the datasheet conflicts with the TRM and generally I always take the datasheet as the overriding buck-stops-here source of information. In this case however, it appeared to me the misinformation is due to a carryover from a previous device in the same family. The previous generation device (DM8148) had two DDR EMIFs with a total of 2GByte address space. Since the DM385 only has one DDR EMIF, I made my assumption based on that.

    What I've done is passed this thread onto our product team to get the definitive answer, they'll likely check with the chip design team to get this information.

    Sorry about the confusion, we'll get this cleared up.

    Regards

  • Hello,

    We are building a new EVM that has the DM388, for DDR3.  In this application we are using (2) DDR3 devices.   MT41K256M16TW - Micron memory.

    dm388_newEVM_DDRschpage.jpg - here is the device used.   These EVMs are being tested in the next month.

    The Micron MT41K256M16 device is being utilized.   It says its a 4Gb, x16 device.  I have attached the datasheet.

    www.micron.com/.../mt41k256m16ha-125

  • Brad,

    Have you heard any update on the RAM options for the DM385? I am needing to pick out my RAM options and it depends on your answer.

    Thank you,

  • Hello Brad,

    What we find in looking at the DM385 datasheet, the front page of the datasheets lists addressing for 2Gbytes of DDR addressing.
    The specifics for the DM385 and DDR3 controller are more limiting:
    1ChipSelect
    4DQS strobes
    16 Row Select addresses (but the controller only supports 15)

    8.13 in the DM385 data sheet

    Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb devices

    dm38x_technicalreferencemanual spruhg 1b

    section 7.2 sizing, RSIZE number of rows, PAGESIZE number of columns, IBANK, EBANK number of chip selects, 15bit address bus (A14.0)

    in looking at the Micron DDR3 device for 4Gbit, Micron_MT41K256M16TW-107_4Gb_DDR3L, Table 2 is important.

    a) if we used (4) x8 DDR3 devices, 512Megx8, the limitation is that we don't use 16 row address lines, only 15, this would actually be 1Gbyte
    b) if we used (1) x16 DDR3 device, 256Megx16 - we would have 512MByte
    c) if we used (2) x16 DDR3 device, 256Megx16 - we would have 1GByte

    In looking at Micron 8Gbit parts, they utilize 2 Chip Selects. (we only have 1)
    In looking at Micron 16Gbit parts, they utilize 16 Row Addresses ( the DDR3 controller only utilizes 15)

    If you could find a DDR3 that utilized 32K Row Address x 8 Bank x 2K column, 1 Chip Select - these fit in the parameters of the DDR controller,
    but I couldn't find one. (For a single x16 this would only be 1GByte)

    Regards,
    Joe Quintal