I have 2 questions.
1. I used Timer 14 in unchained mode where the lower was used as a free-running counter (set the period to FFFFFFFF). The other timer was used to create an interrupt. Since the next time to interrupt was based on a set of decisions, I stopped the timer, computed the new count, populated the period and started it again (all using XDC APIs, not primitively using the memory mapped registers). When I did this, it appeared that the free-running timer stopped as well. This was because as soon as I moved the free-running timestamp to timer 15, it worked without issues. I determined this by checking the TSCL against where I expected the free-running timestamp to be (since the relationship is deterministic at 1/6 of CPU clock). I wonder if there is a bug with the XDC layer. Also, the timer literally took 1.5us before it was received in the HWI. Not sure why (I am planning to benchmark this by primitively running the timer for multiple reasons and will post the results).
2. What is the purpose of RELHI and RELLO? I went and checked a previous version of the document prior to the introduction of TimerPlus mode and it shows that once the period is set and the timer is in continuous mode, it keeps the period and causes an interrupt (as one usecase) every X timercounts. What does the reload register provide in addition? An example would help. I checked the document and did not find any.
