[K2G] 512KB of L2 Memory not existing ?

Hi Rahhul,

Ok, thank you for the clarifications. I had miss understanding about L2 memory.

So how about MSMC SRAM ? That should be regarded as a memory-mapped shared  SRAM on SoC. To me, the definition of MSMCSRAM should be in something xdc script.

The following the script (Mmu.xs) for MMU and it statically configures MMU according to existing memory in Program.cpu.memoryMap.

    /* Make a 1-to-1 mapping of virtual to physical address for memory map */
    var map = Program.cpu.memoryMap;
    for (var i=0; i < map.length; i++) {
        /* Get base address and length and unsigned right shift to get index */
        var start = map[i].base >>> LEVEL2_BLOCK_DESC_SHIFT;
        var end = (map[i].base + map[i].len - 1) >>> LEVEL2_BLOCK_DESC_SHIFT;
        var index = start;
        var attrs = new Mmu.DescriptorAttrs();

        initDescAttrsMeta(attrs);
        attrs.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
        attrs.accPerm = 0;                        // access permissions
        attrs.attrIndx = 2;                       // MAIR0 Byte 1 defines
                                                  // memory region attributes
        attrs.shareable = 3;                      // inner-sharerable

        do {
            /* only set if table descriptor has not been set */
            if ((Mmu.secondLevelTableBuf[index >>> 9][2*(index & 0x1FF)] ==
                        undefined) &&
                (Mmu.secondLevelTableBuf[index >>> 9][2*(index & 0x1FF)+1] ==
                        undefined)) {

                if (Mmu.cachePlatformMemory == true) {
                    setSecondLevelDescMeta(
                            convertToUInt32(index << LEVEL2_BLOCK_DESC_SHIFT),
                            convertToUInt32(index << LEVEL2_BLOCK_DESC_SHIFT),
                            attrs);
                }
                else {
                    setSecondLevelDescMeta(
                            convertToUInt32(index << LEVEL2_BLOCK_DESC_SHIFT),
                            convertToUInt32(index << LEVEL2_BLOCK_DESC_SHIFT),
                            Mmu.defaultAttrs);
                }
            }
            index++;
        } while (index <= end);
    }

 

Because there is no definition of MSMCSRAM in Program.cpu.memoryMap by default, exceptions can happen when accessing MSMCRAM.

Best Regards,
Naoki

typically, TI RTOS will not configure and use Shared memory on the SOC unless explicitly specified by the application developer. The simplest way of using MSMC would be to add a secondary linker command file in the project with the correct section definitions. Please refer to this FAQ TI RTOS question regarding adding more memory sections.
processors.wiki.ti.com/.../BIOS_FAQs

Regards,
Rahul

As a application developer you can also create your own custom platform using the tool described in the section 10.9 in the training slides here:

Hi Rahul,

Yes, i know your points. In fact, I've already defined my own RTSC platform for ARM side because no memory defined except for DDR3. But for DSP side, some internal definitions including MSMC are defined by default . I feel a contradiction at this point.

If you open ti.platforms.evmTCI66AK2G02 for DSP side, you will see the following setup. As you see MSMC has been defined by default.

And if you open ti.platforms.evmTCI66AK2G02 for ARM side, there is no definitions for internal memory.

You say internal shared memory would not be defined typically, but I feel defining all available internal memories would be more appropriate guideline in RTSC point of view.

Anyway, I have no question about L2 memory now. Please input MSMC stuff to your internal team and if required, please consider the fix in the future release. I close the thread now.

Best Regards,
Naoki