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AM437x SPL/u-boot flasher image loading issue using CCS studio.

Hi All,

I am trying to load the U-boot flasher images (SPL and U-boot) using the CCS studio with the help of JTAG interface on to our custom board based on AM437x.

After loading the SPL and U-boot images onto the custom target, u-boot execution was halted as shown in the attached image and not proceeding further.

Did any one see this kind of issues?

Please help me what could be the issue and how can I resolve this issue on our custom platform.


Thanks & Regards

Ch. Siva

  • Hi,

    Did you configure your memory correctly? See this wiki for details: processors.wiki.ti.com/.../AM437x_DDR_Configuration_and_Programming_Guide
  • DDR3_Schematic.pdf

    =~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2016.08.26 10:56:53 =~=~=~=~=~=~=~=~=~=~=~=
    
    LnT: debug func: preload_console_init
    
    U-Boot SPL 2016.05-00230-g5bf448d-dirty (Aug 26 2016 - 10:52:54)
    
    LnT: debug func: preload_console_init
    LNT: func: spl_board_init line:188
    LNT debug spl_board_init
    LNT: func: gpmc_init line:81
    LNT: func: gpmc_init line:103
    LNT: func: gpmc_init line:133
    gpmc_cfg address: 0x80a00000
    gpmc_cfg address: 0x50000000
    gpmc_cfg->sysconfig address: 0x50000010
    gpmc_cfg->irqstatus address: 0x50000018
    gpmc_cfg->irqenable address: 0x5000001c
    LNT: func: gpmc_init line:141
    LNT: func: gpmc_init line:143
    LNT: func: gpmc_init line:145
    LNT: func: gpmc_init line:148
    LNT: func: gpmc_init line:154
    LNT: func: enable_gpmc_cs_config line:56
    LNT: func: enable_gpmc_cs_config line:70
    LNT: func: gpmc_init line:164
    LNT: func: spl_board_init line:192
    LNT: func: spl_board_init line:195
    LNT: func: spl_board_init line:210
    LNT: func : [board_init_r] line [371]
    LNT: func : [board_init_r] line [372] spl_boot_list[0]: [0]
    LNT: func : [board_boot_order] line [195]
    LNT: func: spl_boot_device line:168
    LNT: func : [board_init_r] line [374] spl_boot_list[0]: [0]
    SPL: failed to boot from all boot devices
    ### ERROR ### Please RESET the board ###
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�W���ۀ��ـ�q܀�A܀�=���ހ��ۀ�5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 808357bd
    
    
    U-Boot 2016.05-00230-g5bf448d-dirty (Aug 26 2016 - 10:52:54 +0530)
    
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�ۀ��ـ�q܀�A܀�=���ހ��ۀ�5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080dbbd
    LNT: func: display_text_info line:154
    LNT: func: display_text_info line:162
    LNT: func: display_text_info line:168
    U-Boot code: 80800000 -> 8085A7B0  BSS: -> 808BE5CC
    LNT: func: display_text_info line:179
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�ـ�q܀�A܀�=���ހ��ۀ�5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080d9f9
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [q܀�A܀�=���ހ��ۀ�5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080dc71
    LNT: func: init_func_i2c line:255
    I2C:   ready
    LNT: func: init_func_i2c line:263
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [A܀�=���ހ��ۀ�5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080dc41
    LNT: func: announce_dram_init line:185
    DRAM:  LNT: func: announce_dram_init line:187
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [=���ހ��ۀ�5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 80800b3d
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�ހ��ۀ�5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080de85
    LNT: func: setup_dest_addr line:354
    Monitor len: 000BE5CC
    Ram size: 08000000
    Ram top: 88000000
    LNT: func: setup_dest_addr line:397
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�ۀ�5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080db91
    LNT: func: reserve_round_4k line:443
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [5ۀ��݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080db35
    LNT: func: reserve_mmu line:452
    TLB table from 87ff0000 to 87ff4000
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�݀��ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080ddad
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�ڀ��ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080dad1
    LNT: func: reserve_uboot line:526
    Reserving 761k for U-Boot at: 87f31000
    LNT: func: reserve_uboot line:542
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�ڀ�m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080daa9
    Reserving 16448k for malloc() at: 86f21000
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [m݀��݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080dd6d
    Reserving 80 Bytes for Board Info at: 86f20fb0
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�݀��ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080ddb1
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�ڀ�1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080da81
    Reserving 184 Bytes for Global Data at: 86f20ef8
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [1ڀ��݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080da31
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�݀�߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080dda5
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [߀�Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080df11
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [Qހ��݀�ڀ�A݀��܀�]
    initcall: 8080de51
    LNT: func: setup_dram_config line:734
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�݀�ڀ�A݀��܀�]
    initcall: 8080ddcd
    LNT: func: show_dram_config line:214
    
    RAM Configuration:
    Bank #0: 80000000 128 MiB
    
    DRAM:  128 MiBLNT: func: board_add_ram_info line:141
    
    LNT: func: show_dram_config line:237
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [ڀ�A݀��܀�]
    initcall: 8080da1d
    New Stack Pointer is: 86f20ed0
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [A݀��܀�]
    initcall: 8080dd41
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:21 init_fnc_ptr func: [�܀�]
    initcall: 8080dce9
    Relocation Offset is: 07731000
    Relocating to 87f31000, new gd at 86f20ef8, sp at 86f20ed0
    LNT: func: initcall_run_list line:34 ret: 0
    LNT: func: initcall_run_list line:42
    LNT: func: board_init_f line: 1097 ret_lnt: 0
    
    2806.AM43xx_EMIFconfig_HWlvl.gelHi Biser,

    thanks for the response .. Yes we believe we have done the right configuration. Just to give the background we are using the same DDR3 part that is being used in the EVM, however we have connected only the 13 lines. Attaching the schematics for your reference (please ignore the part number).   Also we are using the attached gel file for the DDR3 configuration. The DDR3 Integrity test  passes with the values used however we see the hang when loading the second stage bootloader. Also attaching the console logs with more debug prints.

    Please review the schematic/the configuration values used are fine and why this issue could happen.

    Best regards,

    Siva

  • Schematic seems OK. I will ask the software team for suggestions what could be wrong.
  • Thanks Biser,

    Could you please also help checking the SDRAM_CONFIG configurations ? We modified the gel file for 16 bit support as given in the link you shared earlier.

    Best Regards,
    Shiv
  • Hi Biser,

    Do you get any update from software team how can we come out from this issue?

    Along with above configurations, we would like to understand the some more registers in the GEL file as shown below. The above all the registers contains the all default values and we did not change.

    #define PHY_CTRL_SLAVE_RATIO 0x80
    #define PHY_GATELVL_INIT_RATIO 0x20
    #define PHY_WRLVL_INIT_RATIO 0x00
    #define PHY_FIFO_WE_IN_DELAY 0x0
    #define PHY_CTRL_SLAVE_DELAY 0x0
    #define PHY_WR_DQS_SLAVE_DELAY 0x60
    #define PHY_GATELVL_INIT_MODE 0x01
    #define PHY_USE_RANKO_DELAYS 0x01
    #define PHY_WR_DATA_SLAVE_DELAY 0x80
    #define PHY_GATELVL_NUM_DQ0 0xF
    #define PHY_WRLVL_NUM_DQ0 0xf

    How does these register values are defined in the GEL file?
    Is these registers are depend on custom board PHY integrity? If yes from where can we get these values?
    How these values are programmed in the u-boot source to generate binary file?

    We appreciate your quick support on this.

    Thanks & Regards
    Ch. Siva
  • Feedback will be posted directly here when available. Response may be delayed due to people being out of office at this time.
  • Hi Biser,

    Did you get any update from your software team regarding issue?

    We are struck in our development at this point and not able to proceed further.

    Kindly please have a look into the issue and provide your valuable suggestions to resolve this issue.

    Thanks in advance!!

    Thanks & Regards

    Ch. Siva

  • Hi Siva,

    Those are bit fields in the EMIF4D_EXT_PHY_CTRL_x (x = 1 to 36). Thy are described in Section 9.3.4.94 through Section Section 9.3.4.165 of AM437x device data manual.

    Also the wiki link, provided by Biser, explains how to set these registers:
    processors.wiki.ti.com/.../AM437x_DDR_Configuration_and_Programming_Guide

    You can see the values of these registers defined in board/ti/am43xx/board.c , search for "ext_phy_ctrl" in the file.

    As for the GEL settings, I see that your gel file is similar to the original AM43xx_EMIFconfig_HWlvl.gel, with the exception that you operate in narrow mode (16-bit) only:
    WR_MEM_32(EMIF_SDRAM_CONFIG_EXT,0x2C163); => you set EMIF_SDRAM_CONFIG_EXT[17]NARROW_ONLY = 0x1

    and you have added a delay
    for (i=0; i<1000; i++) ;
    to ensure the hw initialization completion.

    The narrow_only setting is OK if it matches your hw. As for the initialization try setting a lower delay, maybe just call an empty function, i.e.:
    void foo(void) {
    }

    Best Regards,
    Yordan
  • Team,

    The DDR integrety tests fail at the later addresses of the DDR. Attchaching the test result. Could you please provide some pointers on possible reasons of failure.

    Best Regards,
    Shiv

    CortexA9: Output: ****  AM437x SK EVM Initialization is in progress .......... 
    CortexA9: Output:  **** Device Type: GP
    CortexA9: GEL Output: System input clock is 24MHz
    CortexA9: GEL Output: ****  AM43xx OPP100 with CLKIN=24MHz is in progress ......... 
    CortexA9: GEL Output: 	 ****  Going to Bypass... 
    CortexA9: GEL Output: 	 ****  Bypassed, changing values... 
    CortexA9: Output: 	 ****  Locking PLL
    CortexA9: GEL Output: 	 ****  MPU PLL locked
    CortexA9: GEL Output: 	 ****  Core Bypassed
    CortexA9: GEL Output: 	 ****  Now locking Core...
    CortexA9: GEL Output: 	 ****  Core locked
    CortexA9: GEL Output: 	 ****  Calculated PER SD Divisor=4
    CortexA9: GEL Output: 	 ****  PER DPLL Bypassed
    CortexA9: GEL Output: 	 ****  PER DPLL Locked
    CortexA9: GEL Output: 	 ****  Calculated EXTDEV SD Divisor=4
    CortexA9: GEL Output: 	 ****  EXTDEV DPLL Bypassed
    CortexA9: GEL Output: 	 ****  EXTDEV DPLL Locked
    CortexA9: GEL Output: 	 ****  DISP PLL Config is in progress .......... 
    CortexA9: GEL Output: 	 ****  DISP PLL Locked 
    CortexA9: GEL Output: 	 ****  DDR DPLL Bypassed
    CortexA9: GEL Output: 	 ****  DDR DPLL Locked
    CortexA9: GEL Output: ****  Setting DDR3  = 400MHz
    CortexA9: GEL Output: ****  AM43xx OPP100 configuration is done ......... 
    CortexA9: GEL Output: Starting DDR3 configuration...
    CortexA9: Output: EMIF PRCM is in progress ....... 
    CortexA9: Output: EMIF PRCM Done 
    CortexA9: GEL Output: EMIF CLK enabled... 
    CortexA9: GEL Output: Waiting for VTP Ready ....... 
    CortexA9: GEL Output: VTP is Ready! 
    CortexA9: GEL Output: VTP controller enabled
    CortexA9: GEL Output: Checking if DLL is ready...
    CortexA9: GEL Output: DLL is ready
    CortexA9: GEL Output: Configuring DDR IOs and Control Module registers...
    CortexA9: GEL Output: Configuration of Control Module registers complete
    CortexA9: GEL Output: Setting up DDR3 H/W leveling configuration...
    CortexA9: GEL Output: Starting EMIF controller configuration...
    CortexA9: GEL Output: EVM==2
    CortexA9: GEL Output: 
    
    DDR3 Hardware leveling complete... Outputing all the leveling results !!!
    
    CortexA9: GEL Output: PHY_STATUS_12=0x0700003C
    CortexA9: GEL Output: PHY_STATUS_13=0x07000037
    CortexA9: GEL Output: PHY_STATUS_14=0x07000700
    CortexA9: GEL Output: PHY_STATUS_15=0x07000700
    CortexA9: GEL Output: PHY_STATUS_16=0x00000000
    CortexA9: GEL Output: PHY_STATUS_7 =0x00000047
    CortexA9: GEL Output: PHY_STATUS_8 =0x00000047
    CortexA9: GEL Output: PHY_STATUS_9 =0x00000000
    CortexA9: GEL Output: PHY_STATUS_10=0x00000000
    CortexA9: GEL Output: PHY_STATUS_11=0x00000000
    CortexA9: GEL Output: PHY_STATUS_17=0x0019004B
    CortexA9: GEL Output: PHY_STATUS_18=0x01E5004D
    CortexA9: GEL Output: PHY_STATUS_19=0x0035039D
    CortexA9: GEL Output: PHY_STATUS_20=0x00500369
    CortexA9: GEL Output: PHY_STATUS_21=0x00000000
    CortexA9: GEL Output: PHY_STATUS_22=0x03D9000B
    CortexA9: GEL Output: PHY_STATUS_23=0x01A5000D
    CortexA9: GEL Output: PHY_STATUS_24=0x0035039D
    CortexA9: GEL Output: PHY_STATUS_25=0x00500369
    CortexA9: GEL Output: PHY_STATUS_26=0x00000000
    CortexA9: GEL Output: 
    
    DDR3 configuration is complete!!!
    
    CortexA9: GEL Output: Turning on EDMA...  
    CortexA9: GEL Output: EDMA is turned on...  
    CortexA9: Output: ****  AM437x SK EVM Initialization is Done ****************** 
    
    
    CortexA9: GEL Output: Try Accessing DDR memory....Write data
    CortexA9: GEL Output: Data written at :: 0x86FF0000 
    CortexA9: GEL Output: Data written at :: 0x86FF0004 
    CortexA9: GEL Output: Data written at :: 0x86FF0008 
    CortexA9: GEL Output: Data written at :: 0x86FF000C 
    CortexA9: GEL Output: Data written at :: 0x86FF0010 
    CortexA9: GEL Output: Data written at :: 0x86FF0014 
    CortexA9: GEL Output: Data written at :: 0x86FF0018 
    CortexA9: GEL Output: Data written at :: 0x86FF001C 
    CortexA9: GEL Output: Data written at :: 0x86FF0020 
    CortexA9: GEL Output: Data written at :: 0x86FF0024 
    CortexA9: GEL Output: Data written at :: 0x86FF0028 
    CortexA9: GEL Output: Data written at :: 0x86FF002C 
    CortexA9: GEL Output: Data written at :: 0x86FF0030 
    CortexA9: GEL Output: Data written at :: 0x86FF0034 
    CortexA9: GEL Output: Data written at :: 0x86FF0038 
    CortexA9: GEL Output: Data written at :: 0x86FF003C 
    CortexA9: GEL Output: Data written at :: 0x86FF0040 
    CortexA9: GEL Output: Data written at :: 0x86FF0044 
    CortexA9: GEL Output: Data written at :: 0x86FF0048 
    CortexA9: GEL Output: Data written at :: 0x86FF004C 
    CortexA9: GEL Output: Data written at :: 0x86FF0050 
    CortexA9: GEL Output: Data written at :: 0x86FF0054 
    CortexA9: GEL Output: Data written at :: 0x86FF0058 
    CortexA9: GEL Output: Data written at :: 0x86FF005C 
    CortexA9: GEL Output: Data written at :: 0x86FF0060 
    CortexA9: GEL Output: Data written at :: 0x86FF0064 
    CortexA9: GEL Output: Data written at :: 0x86FF0068 
    CortexA9: GEL Output: Data written at :: 0x86FF006C 
    CortexA9: GEL Output: Data written at :: 0x86FF0070 
    CortexA9: GEL Output: Data written at :: 0x86FF0074 
    CortexA9: GEL Output: Data written at :: 0x86FF0078 
    CortexA9: GEL Output: Data written at :: 0x86FF007C 
    CortexA9: GEL Output: Data written at :: 0x86FF0080 
    CortexA9: GEL Output: Data written at :: 0x86FF0084 
    CortexA9: GEL Output: Data written at :: 0x86FF0088 
    CortexA9: GEL Output: Data written at :: 0x86FF008C 
    CortexA9: GEL Output: Data written at :: 0x86FF0090 
    CortexA9: GEL Output: Data written at :: 0x86FF0094 
    CortexA9: GEL Output: Data written at :: 0x86FF0098 
    CortexA9: GEL Output: Data written at :: 0x86FF009C 
    CortexA9: GEL Output: Data written at :: 0x86FF00A0 
    CortexA9: GEL Output: Data written at :: 0x86FF00A4 
    CortexA9: GEL Output: Data written at :: 0x86FF00A8 
    CortexA9: GEL Output: Data written at :: 0x86FF00AC 
    CortexA9: GEL Output: Data written at :: 0x86FF00B0 
    CortexA9: GEL Output: Data written at :: 0x86FF00B4 
    CortexA9: GEL Output: Data written at :: 0x86FF00B8 
    CortexA9: GEL Output: Data written at :: 0x86FF00BC 
    CortexA9: GEL Output: Data written at :: 0x86FF00C0 
    CortexA9: GEL Output: Data written at :: 0x86FF00C4 
    CortexA9: GEL Output: Data written at :: 0x86FF00C8 
    CortexA9: GEL Output: Data written at :: 0x86FF00CC 
    CortexA9: GEL Output: Data written at :: 0x86FF00D0 
    CortexA9: GEL Output: Data written at :: 0x86FF00D4 
    CortexA9: GEL Output: Data written at :: 0x86FF00D8 
    CortexA9: GEL Output: Data written at :: 0x86FF00DC 
    CortexA9: GEL Output: Data written at :: 0x86FF00E0 
    CortexA9: GEL Output: Data written at :: 0x86FF00E4 
    CortexA9: GEL Output: Data written at :: 0x86FF00E8 
    CortexA9: GEL Output: Data written at :: 0x86FF00EC 
    CortexA9: GEL Output: Data written at :: 0x86FF00F0 
    CortexA9: GEL Output: Data written at :: 0x86FF00F4 
    CortexA9: GEL Output: Data written at :: 0x86FF00F8 
    CortexA9: GEL Output: Data written at :: 0x86FF00FC 
    CortexA9: GEL Output: Data written at :: 0x86FF0100 
    CortexA9: GEL Output: Data written at :: 0x86FF0104 
    CortexA9: GEL Output: Data written at :: 0x86FF0108 
    CortexA9: GEL Output: Data written at :: 0x86FF010C 
    CortexA9: GEL Output: Data written at :: 0x86FF0110 
    CortexA9: GEL Output: Data written at :: 0x86FF0114 
    CortexA9: GEL Output: Data written at :: 0x86FF0118 
    CortexA9: GEL Output: Data written at :: 0x86FF011C 
    CortexA9: GEL Output: Data written at :: 0x86FF0120 
    CortexA9: GEL Output: Data written at :: 0x86FF0124 
    CortexA9: GEL Output: Data written at :: 0x86FF0128 
    CortexA9: GEL Output: Data written at :: 0x86FF012C 
    CortexA9: GEL Output: Data written at :: 0x86FF0130 
    CortexA9: GEL Output: Data written at :: 0x86FF0134 
    CortexA9: GEL Output: Data written at :: 0x86FF0138 
    CortexA9: GEL Output: Data written at :: 0x86FF013C 
    CortexA9: GEL Output: Data written at :: 0x86FF0140 
    CortexA9: GEL Output: Data written at :: 0x86FF0144 
    CortexA9: GEL Output: Data written at :: 0x86FF0148 
    CortexA9: GEL Output: Data written at :: 0x86FF014C 
    CortexA9: GEL Output: Data written at :: 0x86FF0150 
    CortexA9: GEL Output: Data written at :: 0x86FF0154 
    CortexA9: GEL Output: Data written at :: 0x86FF0158 
    CortexA9: GEL Output: Data written at :: 0x86FF015C 
    CortexA9: GEL Output: Data written at :: 0x86FF0160 
    CortexA9: GEL Output: Data written at :: 0x86FF0164 
    CortexA9: GEL Output: Data written at :: 0x86FF0168 
    CortexA9: GEL Output: Data written at :: 0x86FF016C 
    CortexA9: GEL Output: Data written at :: 0x86FF0170 
    CortexA9: GEL Output: Data written at :: 0x86FF0174 
    CortexA9: GEL Output: Data written at :: 0x86FF0178 
    CortexA9: GEL Output: Data written at :: 0x86FF017C 
    CortexA9: GEL Output: Data written at :: 0x86FF0180 
    CortexA9: GEL Output: Data written at :: 0x86FF0184 
    CortexA9: GEL Output: Data written at :: 0x86FF0188 
    CortexA9: GEL Output: Data written at :: 0x86FF018C 
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000000,  Addr:0x86FF0000, Expected: 0xA5A5A5A5, Read: 0x26900890
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000001,  Addr:0x86FF0001, Expected: 0xA5A5A5A5, Read: 0x36B88618
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000002,  Addr:0x86FF0002, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000002,  Addr:0x86FF0003, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000003,  Addr:0x86FF0004, Expected: 0xA5A5A5A5, Read: 0x08804820
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000003,  Addr:0x86FF0005, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000003,  Addr:0x86FF0006, Expected: 0xA5A5A5A5, Read: 0x50883634
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000004,  Addr:0x86FF0007, Expected: 0xA5A5A5A5, Read: 0x10903438
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000004,  Addr:0x86FF0008, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000004,  Addr:0x86FF0009, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000005,  Addr:0x86FF000A, Expected: 0xA5A5A5A5, Read: 0xA478EF22
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000006,  Addr:0x86FF000B, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000006,  Addr:0x86FF000C, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000006,  Addr:0x86FF000D, Expected: 0xA5A5A5A5, Read: 0x04056094
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000006,  Addr:0x86FF000E, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000006,  Addr:0x86FF000F, Expected: 0xA5A5A5A5, Read: 0xAC100623
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000007,  Addr:0x86FF0010, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000007,  Addr:0x86FF0011, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000007,  Addr:0x86FF0012, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000007,  Addr:0x86FF0013, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000008,  Addr:0x86FF0014, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000009,  Addr:0x86FF0015, Expected: 0xA5A5A5A5, Read: 0x8C23F830
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000009,  Addr:0x86FF0016, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000009,  Addr:0x86FF0017, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000A,  Addr:0x86FF0018, Expected: 0xA5A5A5A5, Read: 0x42D21520
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000A,  Addr:0x86FF0019, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000A,  Addr:0x86FF001A, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000A,  Addr:0x86FF001B, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000A,  Addr:0x86FF001C, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000B,  Addr:0x86FF001D, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000C,  Addr:0x86FF001E, Expected: 0xA5A5A5A5, Read: 0x10612C02
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000C,  Addr:0x86FF001F, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000D,  Addr:0x86FF0020, Expected: 0xA5A5A5A5, Read: 0x06282B00
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000D,  Addr:0x86FF0021, Expected: 0xA5A5A5A5, Read: 0x2278127E
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000D,  Addr:0x86FF0022, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000E,  Addr:0x86FF0023, Expected: 0xA5A5A5A5, Read: 0x209BB220
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000E,  Addr:0x86FF0024, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000E,  Addr:0x86FF0025, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000F,  Addr:0x86FF0026, Expected: 0xA5A5A5A5, Read: 0x20184479
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000000F,  Addr:0x86FF0027, Expected: 0xA5A5A5A5, Read: 0x2099000D
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000010,  Addr:0x86FF0028, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000011,  Addr:0x86FF0029, Expected: 0xA5A5A5A5, Read: 0xA0318820
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000011,  Addr:0x86FF002A, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000011,  Addr:0x86FF002B, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000012,  Addr:0x86FF002C, Expected: 0xA5A5A5A5, Read: 0x79B000A8
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000012,  Addr:0x86FF002D, Expected: 0xA5A5A5A5, Read: 0xAC84DA00
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000012,  Addr:0x86FF002E, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000013,  Addr:0x86FF002F, Expected: 0xA5A5A5A5, Read: 0x0E930212
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000014,  Addr:0x86FF0030, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000015,  Addr:0x86FF0031, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000016,  Addr:0x86FF0032, Expected: 0xA5A5A5A5, Read: 0x08480EA8
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000016,  Addr:0x86FF0033, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000017,  Addr:0x86FF0034, Expected: 0xA5A5A5A5, Read: 0x828C1090
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000018,  Addr:0x86FF0035, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000018,  Addr:0x86FF0036, Expected: 0xA5A5A5A5, Read: 0x46B90828
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000019,  Addr:0x86FF0037, Expected: 0xA5A5A5A5, Read: 0x20212B20
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001A,  Addr:0x86FF0038, Expected: 0xA5A5A5A5, Read: 0x6C88C600
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001A,  Addr:0x86FF0039, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001A,  Addr:0x86FF003A, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001A,  Addr:0x86FF003B, Expected: 0xA5A5A5A5, Read: 0x69507D21
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001B,  Addr:0x86FF003C, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001C,  Addr:0x86FF003D, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001D,  Addr:0x86FF003E, Expected: 0xA5A5A5A5, Read: 0x6210E027
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001D,  Addr:0x86FF003F, Expected: 0xA5A5A5A5, Read: 0x34A31E46
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001E,  Addr:0x86FF0040, Expected: 0xA5A5A5A5, Read: 0x8E75509B
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001F,  Addr:0x86FF0041, Expected: 0xA5A5A5A5, Read: 0x06D60C18
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000001F,  Addr:0x86FF0042, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000020,  Addr:0x86FF0043, Expected: 0xA5A5A5A5, Read: 0x84F40422
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000021,  Addr:0x86FF0044, Expected: 0xA5A5A5A5, Read: 0x09A24468
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000022,  Addr:0x86FF0045, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000022,  Addr:0x86FF0046, Expected: 0xA5A5A5A5, Read: 0x00308688
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000022,  Addr:0x86FF0047, Expected: 0xA5A5A5A5, Read: 0x4161A300
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000023,  Addr:0x86FF0048, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000024,  Addr:0x86FF0049, Expected: 0xA5A5A5A5, Read: 0x0C1966A0
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000024,  Addr:0x86FF004A, Expected: 0xA5A5A5A5, Read: 0x0D843761
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000025,  Addr:0x86FF004B, Expected: 0xA5A5A5A5, Read: 0x04901885
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000025,  Addr:0x86FF004C, Expected: 0xA5A5A5A5, Read: 0x14252A32
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000025,  Addr:0x86FF004D, Expected: 0xA5A5A5A5, Read: 0x20357E00
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000026,  Addr:0x86FF004E, Expected: 0xA5A5A5A5, Read: 0x090A0214
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000026,  Addr:0x86FF004F, Expected: 0xA5A5A5A5, Read: 0x8A0516B8
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000027,  Addr:0x86FF0050, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000027,  Addr:0x86FF0051, Expected: 0xA5A5A5A5, Read: 0x20E1207C
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000028,  Addr:0x86FF0052, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000029,  Addr:0x86FF0053, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002A,  Addr:0x86FF0054, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002B,  Addr:0x86FF0055, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002B,  Addr:0x86FF0056, Expected: 0xA5A5A5A5, Read: 0x35852205
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002C,  Addr:0x86FF0057, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002C,  Addr:0x86FF0058, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002D,  Addr:0x86FF0059, Expected: 0xA5A5A5A5, Read: 0x0C578D01
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002D,  Addr:0x86FF005A, Expected: 0xA5A5A5A5, Read: 0x24216CF1
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002E,  Addr:0x86FF005B, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002F,  Addr:0x86FF005C, Expected: 0xA5A5A5A5, Read: 0x0453A820
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002F,  Addr:0x86FF005D, Expected: 0xA5A5A5A5, Read: 0x2CF1AC40
    CortexA9: GEL Output: No of Failed locations  are :: 0x0000002F,  Addr:0x86FF005E, Expected: 0xA5A5A5A5, Read: 0x058814EC
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000030,  Addr:0x86FF005F, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000031,  Addr:0x86FF0060, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000031,  Addr:0x86FF0061, Expected: 0xA5A5A5A5, Read: 0xA920BB19
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000032,  Addr:0x86FF0062, Expected: 0xA5A5A5A5, Read: 0x07684E70
    CortexA9: GEL Output: No of Failed locations  are :: 0x00000032,  Addr:0x86FF0063, Expected: 0xA5A5A5A5, Read: 0xA5A5A5A5
    CortexA9: GEL Output: Data Integrity check Failed

  • Shiv, a couple of questions:

    1. Earlier in the post, you said that the integrity test passed, but then later it failed. What changed between the two.
    2. Can you try with invert_clkout=1. Note you have to make 2 changes in the GEL for this. See section "Proper initialization for DDR3 H/W leveling" in the following wiki: processors.wiki.ti.com/.../AM437x_DDR_Configuration_and_Programming_Guide

    3. Once you have it stable thru JTAG in CCS, then make the appropriate changes in SPL and try it there. If it still doesn't boot, you can perform a register dump of the EMIF registers and compare with the working register dump from the GEL

    Regards,
    James
  • -------- Original Message --------
    From: "Nagalikar, Shivasharan" <
    shivasharan.nagalikar@ti.com>
    Date: Thu 15 Sep, 2016, 10:27 PM
    To: "Doublesin, James" <
    doublesin@ti.com>
    Subject: Fwd: Sitara Processors Forum: AM437x SPL/u-boot flasher image loading issue using CCS studio.

    James, not able to reply on e2e from mobile, sorry.. initially they checked only address 0x80000000 and some 500 locations only which was passing. Then they thought that DDR was done bit booting its failing. When I tried investing checked higher address locations and it's failing there. With invert clock 1 also I have tried. So nothing has changed between two only that they concluded without testing completely.

    Best regards,
    Shiv

  • Shiv, the output of the GEL shows this line:

    CortexA9: GEL Output: EVM==2


    Which means it will use

    #define IDK_EVM_DDR3_SDRAM_CONFIG     0x61A11B32  //32-bit DDR3

    I think you intended to use this SDRAM_CONFIG register definition

    #define DDR3_SDRAM_CONFIG       0x61A05232  //16-bit DDR3

    I would double check in CCS memory window what the SDRAM_CONFIG register is getting set to.  Based on the output of the memory test, I think all of your timing is setup correctly, but the DDR configuration is not correct (as dictated by SDRAM_CONFIG register)

    Regards,

    James

  • Hi James,

    Yes that value is also tried and it did not help.

    Best Regards,

    Shiv

  • Hi,

    I also had the same problem with a similar processor. The U-Boot was running fine, when it was loaded from eMMC, but stopped at the same point when it was loaded with JTAG from CCS.
    The solution was to build U-Boot with CONFIG_SYS_DCACHE_OFF define enabled to disable using data cache.

    I guess you could get over it by now, but it might be helpful for someone having the same problem.

    Regards,
    David