I have a question about IDLE of C5505

Hi!

My customers to use the C5505, is under development.
When they have confirmed Idle, problems occurred.

C5505 will enter the power down in PCGCRx or PCGCRn and ICR + idle instruction.

In two cases, the difference of about 1.3mA when measured current has occurred. The reason for this difference?

Case 1. After setting the PCGCRn, it was stopped the set to clock the SYSCLKDIS.

Case 2. After setting the PCGCRn, without setting a SYSCLKDIS, stopped the clock in the ICR + Idle instruction.

*The difference forms in the case when the next order is executed and the case which isn't done. /* System clock disabled */
CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_SYSCLKDIS, DISABLED);

<Source code>
void xxx_Sleep(void)
{
    Uint16 reg;

    /* Stop UART clock */
    reg = CSL_SYSCTRL_REGS->CLKSTOP;
    reg |= CSL_SYS_CLKSTOP_URTCLKSTPREQ_MASK;
    CSL_SYSCTRL_REGS->CLKSTOP = reg;
    while (CSL_FEXT(CSL_SYSCTRL_REGS->CLKSTOP, SYS_CLKSTOP_URTCLKSTPACK)==0);

    /* Disable the UART clock */
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_UARTCG, DISABLED);

    /* Disable the I2C clock */
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_I2CCG, DISABLED);
    /* Disable the SPI clock */
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_SPICG, DISABLED);
    /* Disable the I2S clock */
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_I2S0CG, DISABLED);
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_I2S1CG, DISABLED);
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_I2S2CG, DISABLED);
    /* Disable the Timer clock */
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_TMR0CG, DISABLED);
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_TMR1CG, DISABLED);
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_TMR2CG, DISABLED);
    /* Disable the DMA0, DMA1, DMA2, DMA3 clock */
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_DMA0CG, DISABLED);
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR2, SYS_PCGCR2_DMA1CG, DISABLED);
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR2, SYS_PCGCR2_DMA2CG, DISABLED);
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR2, SYS_PCGCR2_DMA3CG, DISABLED);

    /* Force to BYPASS mode */
    CSL_FINST(CSL_SYSCTRL_REGS->CCR2, SYS_CCR2_SYSCLKSEL, BYPASS);

    /* PLL stop*/
    CSL_SYSCTRL_REGS->CGCR1 = 0xA27C;

    /* System clock disabled */
    CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_SYSCLKDIS, DISABLED);

    /* set CPUI bit in ICR */
    *(ioport volatile unsigned int *)(0x0001) = 0x03EF;

    CSL_CPU_REGS->IFR0 = 0xFFFF;
       CSL_CPU_REGS->IFR1 = 0xFFFF;

    C55_disableIER0( C55_IFG02 );    /* INT0 */
    C55_disableIER0( C55_IFG03 );    /* INT1 */
    C55_disableIER0( C55_IFG04 );    /* TINT */
    C55_disableIER0( C55_IFG08 );    /* DMA */
    C55_disableIER1( C55_IFG018 );    /* Wakeup */

    /* Go to sleep */
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" idle");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
       asm(" NOP");
}

In the figure below, to set the SYSCLKDIS, not difference of 1.3mA has occurred.

* CLKOUT was turned off, but an electric current didn't fall so much.

Regards,

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

I have notified our experts on the above. They will get back to you. Thank you.

0 Vasantha K over 9 years ago in reply to Raja

TI__Genius 12575 points

Hi,

Could you let us know the idle power number that you measured? Did you compare your power numbers with power spread sheet ? It would be interesting to know if the data is aligned with power spreadsheet idle power data.

Did you try idle scenarios using CSL example provided in CSL 3.06 package, can you confirm ?

Also, I could not completely Understand your 2nd case statement, Could you please provide more details your 2nd case statement: This would help us in better answering your questions.

Case 1. After setting the PCGCRn, it was stopped the set to clock the SYSCLKDIS.
Case 2. After setting the PCGCRn, without setting a SYSCLKDIS, stopped the clock in the ICR + Idle instruction.

Regards

Vasanth

0 da over 9 years ago in reply to Vasantha K

Expert 2780 points

Hi!

Thanks your Reply.

> Could you let us know the idle power number that you measured?

case 1
PCGCRn set only
0.47mA

case 2
PCGCRn(without SYSCLKDIS) + Run Idle instruction
1.74mA

In the source code, CLKOFF has not been set.
However, those this number being set.

> spread sheet ....
CVdd = 1.4v / DVdd = 3.3v / LDOI = 1.8v /Standby mode = 1.59 mW

0.47mA * 3.3v = 1.551 mW? ... same
1.74mA * 3.3v = 5.742 mW? ... too many

> Also, I could not completely Understand your 2nd case statement

Please refer to the source code of the first question.
Not to run a "red-letter code" is the case 2.

case 1
:
/* System clock disabled */
CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_SYSCLKDIS, DISABLED);
:

case 2
:
/* System clock disabled */
// CSL_FINST(CSL_SYSCTRL_REGS->PCGCR1, SYS_PCGCR1_SYSCLKDIS, DISABLED);
:

Regard,
Da

0 Vasantha K over 9 years ago in reply to da

TI__Genius 12575 points

Hi,

Thanks for providing the information.

The Idle3 current you are observing almost aligns with the power spreadsheet, which is ~0.6 mA, which is typical power number. Below is the snapshot for your reference.

Your below power calculation looks not correct,

0.47mA * 3.3v = 1.551 mW? ... same
1.74mA * 3.3v = 5.742 mW? ... too many

For calculation of power in mW, you multiply Core voltage with core current , IO voltage with IO current ... and sum of all will result power in mW.

Snapshot below depicts power in mW based on the above calculations.

Hope this clarifies.

To further analyze your case 2 , I need few more information

What is the clock source is it internal or external ? If external what is the frequency of the external clock source?

Regards

Vasanth

0 da over 9 years ago in reply to Vasantha K

Expert 2780 points

Hi Vasanth

> What is the clock source is it internal or external ? If external what is the frequency of the external clock source?

Case 1 and Case 2 is the same clock source and frequency.
Will there this much difference in internal and external?

By the difference besides the blue parts.
Will it be such difference?
Is there a part which isn't turned off yet?

case 1

case 2

Regards,
Da

0 da over 9 years ago in reply to da

Expert 2780 points

PCR2 [DMA3CG] also has to OFF.

0 Vasantha K over 8 years ago in reply to da

TI__Genius 12575 points

Hi,

To Clarify,

In case1 since you switch of the System clock the clock frequency doesn’t matter. In case 2 your system clock is not disabled, but you are executing idle instruction, that’s the reason I was checking with you on the source and frequency of the clock. Assuming the clock source is external clock and frequency to be 12 MHz, then the current measured is ~1.3mA (2.50mW) as per the powerspreadsheet . If your case2 scenario is same as this then, what you are observing seems correct.

With respect to your question “Is there a part which isn't turned off yet? - If you have taken care of disabling the clocks in PCGCR, then it should be correct, the clocks to respective peripherals would get disabled.

Also, just curious to know from you, the reason for considering case 2 – why wouldn’t you use case1, which is idle3 mode ?

Regards

Vasanth

0 da over 8 years ago in reply to Vasantha K

Expert 2780 points

Hi,

(Because I heard a different reason ...)

They want to know why there is a difference to the clock by comparing the case1 and case2 there is no block being supplied.

In between the other of the gate from SYSCLKDIS in case2, much whether current is needed?

Regard,

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I have a question about IDLE of C5505