Timer PLUS in OMAPL138

Marc48067

Expert 2000 points

Other Parts Discussed in Thread: OMAPL138

Hello,

I have some simple questions concerning the timer plus functionality in the OMAPL138. Formerly we used a timer in the DM642 which sends an edma event when the count register reaches the value in the period register. The Timer is reset and continues counting. The edma reloads the count register with a value out of a table in memory (no reload register available). Now we want to do the same with the timer plus in the OMAPL138. My questions are:

- Do we need the timer plus functionality (reload,...) to achieve the functionality described above?

- Are we allowed to write to the timer counter register while the timer is running (plus features disabled)? (see 2.1.5.2 of sprufm5a)

- Is it necessary to acknowledge the edma event in INTCTLSTAT? In the dm642 there was no need to acknowledge the edma event.

Thanks for your help

over 15 years ago

0 tlee over 15 years ago

TI__Guru 62975 points

Marc said:

- Do we need the timer plus functionality (reload,...) to achieve the functionality described above?

Yes, the reload function would be the way to do this

Marc said:

- Are we allowed to write to the timer counter register while the timer is running (plus features disabled)? (see 2.1.5.2 of sprufm5a)

Officially, the TIM count registers are always locked when the timer is running, but a feature of the continuous reload mode is that the TIM count registers are writeable.

Marc said:

- Is it necessary to acknowledge the edma event in INTCTLSTAT? In the dm642 there was no need to acknowledge the edma event.

My understanding is that it should not be necessary to acknowledge the EDMA event.

0 Christian Rückl over 12 years ago in reply to tlee

Intellectual 340 points

Hi,

regarding the last answer in the post before. Can anybody confirm that, that it isn't necessary to acknowledge/reset the corresponding bit in the INTCTLSTAT register. At the moment I have exactly this problem, that my timer shall trigger every match of the PRD and TIM register a DMA event but an event is only submitted to the EDMA controller when the CPU was setting the corresponding bit in INTCTLSTAT to 0. Is there something wrong in my timer configuration? I'm using only Timer 12... below all the necessary timer configuration registers:

TCR 0x000000F3 Memory Mapped Register: Timer Control Register

_RSVD ******

READRSTMODE34 0 - CONTINUE Determines the effect of a timer counter read on TIMx

TIEN34 0 - NOTGATED Determines if clock is gated by timer input when CLKSRC=0

_RSVD *

ENAMODE34 00 - DISABLE Determines enabling modes of the timer

_RSVD ********

CAPEVTMODE12 00 - RISE Determines event generation from TINP12 when CAPMODE12 = 1; INVINP does not effect edge detection.

CAPMODE12 0 - DISABLE Determines whether the timer is to be run in capture mode or not

READRSTMODE12 0 - CONTINUE Determines the effect of a timer counter read on TIMx

TIEN12 0 - NOTGATED Determines if clock is gated by timer input when CLKSRC=0

CLKSRC12 0 - INTERNAL Determines the selected clock source for timer

ENAMODE12 11 - EN_CONTRELOAD Determines enabling modes of the timer

PWID12 11 - FOUR_CLK Pulse width when CP=0

CP12 0 - PULSE Clock pulse mode for timer output

INVINP12 0 - NON_INVERTED Timer input inverter control when CLKSRC=1

INVOUTP12 1 - INVERTED Timer output inverter control

TSTAT12 1 - HIGH Timer status; Value of timer output; Inverted by INVOUTP

TGCR 0x00000015 Memory Mapped Register: Timer Global Control Register

_RSVD ****************

TDDR34 0000 Linear divide-down ratio for TIM34

PSC34 0000 Pre-scalar counter for TIM34

_RSVD ***

PLUSEN 1 - ENABLE Enables Plus features

TIMMODE 01 - 32BIT_UNCHAIN Determines timer modes

TIM34RS 0 - RESET TIM34 reset

TIM12RS 1 - NO_RESET TIM12 reset

INTCTLSTAT 0x00000003 Memory Mapped Register: Timer interrupt control and status register

_RSVD * Used for test purposes to pulse the interrupt regardless of interrupt settings

_RSVD * Used to pulse the interrupt only if it is enabled

_RSVD **********

EVTINTSTAT34 0 - NOPEND Interrupt status for external event causing a timeout when CAPMODE=1 & BW_COMPATIBLE=1

EVTINTEN34 0 - DISABLE Enables interrupt generation for when an external event causes a timeout & CAPMODE=1 & BW_COMPATIBLE=1

PRDINTSTAT34 0 - NOPEND Interrupt status for TIM vs PRD

PRDINTEN34 0 - DISABLE Enables interrupt generation for TIM vs PRD when BW_COMPATIBLE=1

_RSVD * Used for test purposes to pulse the interrupt regardless of interrupt settings

_RSVD * Used to pulse the interrupt only if it is enabled

_RSVD **********

EVTINTSTAT12 0 - NOPEND Interrupt status for external event causing a timeout when CAPMODE=1 & BW_COMPATIBLE=1

EVTINTEN12 0 - DISABLE Enables interrupt generation for when an external event causes a timeout & CAPMODE=1 & BW_COMPATIBLE=1

PRDINTSTAT12 1 - PEND Interrupt status for TIM vs PRD

PRDINTEN12 1 - ENABLE Enables interrupt generation for TIM vs PRD when BW_COMPATIBLE=1

Thanks for helping me to understand this!

Christian

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Timer PLUS in OMAPL138