Other Parts Discussed in Thread: OMAPL138
Hi.
We have a custom OMAPL-132 board with Micron NAND MT29F1G08ABBDAHC. On some of our boards we encountered nand read and bad blocks failures. We currently have the nand partitioned with UBIFS, JFFS2 partitions and raw data.
I have a few questions that is unclear to me:
1) Subpages, Is there support for it? In the code i can see that it is supported (uboot and kernel), but in http://processors.wiki.ti.com/index.php/Linux_Core_NAND_User's_Guide It says subpages are not supported. What is right then??
2) ECC: What is the correct mode HW_ECC_OOB_FIRST or just HW_ECC? i saw nowhere a reference for the difference and when to use each of them
3) Layout: L-132 Reference Manual says it supports 4-bit Reed-Solomon ECC code, Micron page here: https://www.ece.umd.edu/~blj/CS-590.26/micron-tn2919.pdf says that 72 bits (for 512 bytes i assume) are needed. That makes 9bytes*4areas = 36 bytes for ECC. Another 8 bytes i reserve for JFFS2, now what about the bad block marker? Page 73 in Micron datasheet shows a spare area layout with 2 reserved bad block bytes per 512 bytes. That sounds weird, shouldn't it be like this only when using on-die ECC is used and in my case bad-block table should be stored in last page of nand? So i am a bit of confused on what the correct layout should be...
https://www.micron.com/~/media/documents/products/technical-note/nand-flash/tn2959_bbm_in_nand_flash.pdf Page here says
For SLC large page (2112-byte/1056-word page) devices, any block where the first and sixth bytes (x8 device)/first word (x16 device) in the spare area of the first page does not contain FFh is a bad block.
In uboot code in nand_base.c:
if (!(busw & NAND_BUSWIDTH_16) &&
*maf_id == NAND_MFR_STMICRO &&
mtd->writesize == 2048) {
MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: setting opt NAND_BBT_SCANBYTE1AND6\n", __func__);
chip->options |= NAND_BBT_SCANBYTE1AND6;
chip->badblockpos = 0;
}
This code is never reached, so this option is off by default... Should i change that??
Also from nand_base.c:
/*
* Bad block marker is stored in the last page of each block
* on Samsung and Hynix MLC devices; stored in first two pages
* of each block on Micron devices with 2KiB pages and on
* SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
* only the first page.
*/
if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
(*maf_id == NAND_MFR_SAMSUNG ||
*maf_id == NAND_MFR_HYNIX))
chip->options |= NAND_BBT_SCANLASTPAGE;
else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
(*maf_id == NAND_MFR_SAMSUNG ||
*maf_id == NAND_MFR_HYNIX ||
*maf_id == NAND_MFR_TOSHIBA ||
*maf_id == NAND_MFR_AMD)) ||
(mtd->writesize == 2048 &&
*maf_id == NAND_MFR_MICRON)) {
MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: setting opt NAND_BBT_SCAN2NDPAGE\n", __func__);
chip->options |= NAND_BBT_SCAN2NDPAGE;
}
But in: http://www.linux-mtd.infradead.org/nand-data/nanddata.html It says
Micron MT29F1G08ABBDA 0x2C 0xA1 0x2CA1801502 128 2048 64 128 KB x8 1.0 1st page (1st byte in OOB = non FFh)
So It seems that the driver is definitely configuring badly the nand device. Am i right here?
Are there any patches?
Using u-boot-2012.04.01-psp03.22.00.06.sdk
Thanks a lot
MoonDrop
