bare metal inter processor communication in general

Hannan Khan

hi again !!

i have been searching for ways to communicate between baremetal A15 cores on my K2E.

After reading a couple of application notes and forum post i have come to deduce that the processors place data on the on chip memory and create a single bit in memory to notify read and write operations. My question is that why do we not use the L2 cache for this purpose(or should we use L2?) and is there any other way to communicate between cores?

in my mind i have created the following setup

cores->L2Sram->OCM<-DSP processor
OCM->RAM

thanks !!

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Hi Hannan Khan,

As per my understanding, we do not have bare metal IPC example for this purpose. I will ask our IPC experts to comment here. Thank you for your patience.

0 Shankari G over 9 years ago

TI__Mastermind 43955 points

HI Hannan,

As Raja already said, there are no bare metal examples for IPC. But in the processor SDK, we have good working examples of IPC which runs on top of Linux.

I have personally written an user guide on how to run the IPC examples on Keyston-II devices. Find the user guide as an attachment here.

Try it out and let me know how it goes for you.

Keystone II-IPC Manual.zip

0 Rahul Prabhu over 9 years ago

TI__Guru** 116170 points

If you are talking about using ARM L2 for IPC then this is not possible the A15 architecture typically configures L1 and L2 as full cache and maintains cache coherency between L1 and L2 memory at all times so that memory can`t be used as data to pass information to the DSP. Also, it is my understanding from the spec that ARM has access to DSP L2 memory but the DSP doesn`t have access to ARM L2. Hence you will need to use MSMC or DDR to pass data buffers between the ARM and the DSP.

Hope this answers your question regarding baremetal implementation of IPC mechanism.

Regards,
Rahul

0 Hannan Khan over 9 years ago in reply to Rahul Prabhu

Expert 1080 points

hi !! my question actually was between "baremetal A15 cores on my K2E"

let me explain a bit... i am trying to communicate basic data from my A15 core 0 to core 1 by selecting a memory region and then trying to access data from 2 different cores.... my problem comes in 2 parts

1. if i try to place data in L2 the data fails to show up, i.e. the placement never takes place

2. if i try to place data in MSMC the placement is successful when both programs are run separately but when i run them together in 2 different cores, 1 core dominates the other and doesn't let the other place the data correctly (which i figure is due to shared bus).

i apologize for the confusion earlier !!

just for reference this is my linker mem config

	
	 MEMORY
	 {
	 L2SRAM :       o = 0x00800000,  l = 0x00400000
	 MSMC_SRAM :       o = 0x0c000000,  l = 0x00200000
	 DDR0 :       o = 0x80000000,  l = 0x01000000
	 }

0 Hannan Khan over 9 years ago in reply to Hannan Khan

Expert 1080 points

any update would be appreciated !!

0 Hannan Khan over 9 years ago in reply to Rahul Prabhu

Expert 1080 points

MSMC & DDR ipc was a success.... my problem was that i was using the same block of RAM to load both the code.... obvious mistake i know

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bare metal inter processor communication in general