How to reduce the GPMC operating frequency of AM335x

RAI SANTOSH

Intellectual 520 points

Other Parts Discussed in Thread: AM3352

In My System I have connected TI-DSP 5502 HPI interface with the AM3352 GPMC module.

TI-DSP 5502 HRDY pin is connected with the Wait pin of the AM3352 Processor.

We have configured the GPMC module Chip select 2 with the Asynchronous interface and with Low polarity wait signal.

In normal case the Read and Write operation with the TI-DSP is working fine.

In same case data read by the Processor is not perfect

So to analysis the issue in more detailed I want to reduce the clock frequency of the the GPMC module.

As mention in the data sheet GMPC clock is CORE_CLKOUTM4/2

So is there any way I can able to reduce the operating frequency of the GPMC module.

Please provide me the detailed

I am using the uboot: u-boot-2013.01.01

Linux kernal: Kernel-3.14.26

Regards

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

You have to set the GPMCFCLKDIVIDER bitfield in your GPMC_CONFIG1_2 register. See section 7.1.5.31 in the AM335x TRM Rev. N for details.

0 RAI SANTOSH over 9 years ago in reply to Biser Gatchev-XID

Intellectual 520 points

As mention in the Data Sheet Topic 7.1.3.3.1 GPMC_CLK is Divided using the GPMC_CONFIG1_i[1-0] bit.
This will change the clock frequency of the Synchronous Device Interface.

I have configured the Chip select2 to operate as Asynchronous so it will operate with GPMC_FCLK
which is derived from the CORE_CLKOUTM4/2

So Is there any way to change it

Regards

0 Biser Gatchev-XID over 9 years ago in reply to RAI SANTOSH

TI__Guru**** 393215 points

Nevertheless GPMCFCLKDIVIDER should work for your case too. Another way is described in section 7.1.2.3.8.3.8:

Slow Device Support (TIMEPARAGRANULARITY Parameter)
All access-timing parameters can be multiplied by 2 by setting the GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY bit. Increasing all access timing parameters allows support of slow devices.

0 RAI SANTOSH over 9 years ago in reply to Biser Gatchev-XID

Intellectual 520 points

I have set the GPM0C_CONFIG1[1-0]bit to 11 and measure the chip select width but chip select width is Remain as it is.
Chip select width is not increase as compared the the chip select width when GPMC_CNFIG1[1-0]bit are set to 0.

From that I have conclude that GPM0C_CONFIG1[1-0] bit does not impact the asynchronous interface.
This way is not help full to me.

Second approach which you have mention is all clock are multiplied by 2 by setting GPMC_CONFIG1_i[4] bit.
I have already tested the system by implementing the Multiplied by 2 factor.

GPMC module clock frequency is 100MHz (CORE_CLKOUTM4/2 )
So using this I can able to generate the chip select width Maximum up to 500 - 600ns.

I want to set the timing of chip select more then the 1us to 5us.
So can you please provide me the way

Regards

0 Biser Gatchev-XID over 9 years ago in reply to RAI SANTOSH

TI__Guru**** 393215 points

RAI SANTOSH said:
I want to set the timing of chip select more then the 1us to 5us.

This is not possible.

0 Biser Gatchev-XID over 9 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

You can also check this wiki, perhaps you may find it useful: processors.wiki.ti.com/.../AM335x_GPMC_to_OMAP-L13x_HPI_Interface

0 RAI SANTOSH over 9 years ago in reply to Biser Gatchev-XID

Intellectual 520 points

Hi Biser,

Is there any other way to reduce the GPMC module clock frequency?
Clock is derived from CORE_CLKOUTM4/2 - so what is the possibility to change CORE_CLKOUTM4 frequency

Possible then provide me the configuration register which I need to change

0 Biser Gatchev-XID over 9 years ago in reply to RAI SANTOSH

TI__Guru**** 393215 points

If you try to change the CORE_CLKOUTM4 this will affect multiple other frequencies inside the device, which will cause improper functioning. See Figure 8-10 in the AM335x TRM Rev. N.

0 RAI SANTOSH over 9 years ago in reply to Biser Gatchev-XID

Intellectual 520 points

I have gone through the mention 8-10 block and does not able to derive if I cange the CORE_CLKOUTM4 then which other peripheral clock frequency is change.

Can you please provide me the detailed about it.

Also can you please provide me the configuration Register using which I can able to change the CORE_CLKOUTM4.

I am using Uboot: u-boot-2013.01.01.-pspo5.07.00.00

Linuk kernel : Kernel-3.14.26

I which location I need to make the clock frequency changes

Regards,

0 Biser Gatchev-XID over 8 years ago in reply to RAI SANTOSH

TI__Guru**** 393215 points

To change this clock will mean that you change the CorePLL HS divider M4 clock, which is 200MHz. This will affect the L3 and L4 interconnect clocks directly. I cannot predict what may happen if you slow down the interconnects. The register is CM_DIV_M4_DPLL_CORE.

0 RAI SANTOSH over 8 years ago in reply to Biser Gatchev-XID

Intellectual 520 points

Hi

Can you please provide me the exact file and location of the CM_DIV_M4_DPLL_CORE
in the u-boot source code or in the linux kernel source code

0 RAI SANTOSH over 8 years ago in reply to Biser Gatchev-XID

Intellectual 520 points

Can you please provide me the exact place in the which file and code

I am using Uboot: u-boot-2013.01.01.-pspo5.07.00.00

Linuk kernel : Kernel-3.14.26

I which location I need to make the clock frequency changes in uboot or linux

Regards

0 RAI SANTOSH over 8 years ago in reply to Biser Gatchev-XID

Intellectual 520 points

Can you please provide me the exact file location to change the CM_DIV_M4_DPLL_CORE value
It is in the U-boot or kernel code

I am using Uboot: u-boot-2013.01.01.-pspo5.07.00.00
Linuk kernel : Kernel-3.14.26

0 Biser Gatchev-XID over 8 years ago in reply to RAI SANTOSH

TI__Guru**** 393215 points

I have already asked the software team to do this. They will respond directly here.

0 Yordan Kovachev over 8 years ago in reply to Biser Gatchev-XID

TI__Guru**** 161600 points

Hi,

By grepping the kernel sources, you'll see that you need to modify the am335x clock structure.. the register is defined in arch/arm/mach-omap2/cm33xx.h. Then you need to modify:

arch/arm/mach-omap2/clockdomains33xx_data.c

arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

arch/arm/mach-omap2/omap_hwmod_33xx_data.c

In u-boot a simple git grep of the sources shows that the CM_DIV_M4_DPLL_CORE is set in arch/arm/cpu/armv7/omap4/prcm-regs.c:
.cm_div_m4_dpll_core = 0x4a004138,

Best Regards,

Yordan