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NTSC TV OUT

sairam
Prodigy 150 points
Other Parts Discussed in Thread: SYSCONFIG

Hi All ,

We are trying to display (640x482) resolution image on Television.

TV out of OMAP is configured for NTSC .

We are able to adjust all our applications to fit with in 640x482 Frame buffer , but we are unable to adjust the vertical front poch and back poch.

The following are our register settings in linux kernel . If any of you guys have some kind of application / code to adjust the back and front poches for the above resolution , that will be great help for us .

 

.f_control                              = 0,
        .vidout_ctrl                            = 1,
        .sync_ctrl                              = 0x1040, // Prev 8040
        .llen                                   = 0x359,
        .flens                                  = 0x20C,
        .hfltr_ctrl                             = 0,
        .cc_carr_wss_carr                       = 0x043F2631,
        .c_phase                                = 0,
        .gain_u                                 = 0x102,
        .gain_v                                 = 0x16C,
        .gain_y                                 = 0x12F,
        .black_level                            = 0x43,
        .blank_level                            = 0x38,
        .x_color                                = 0x40,//prev 7
        .m_control                              = 0x1,
        .bstamp_wss_data                        = 0x38,
        .s_carr                                 = 0x21F07C1F,
        .line21                                 = 0,
        .ln_sel                                 = 0x01310011,
        .l21__wc_ctl                            = 0x0000F003,
        .htrigger_vtrigger                      = 0,
        .savid__eavid                           = 0x069300F4,
        .flen__fal                              = 0x0016020C,
        .lal__phase_reset                       = 0x00060107,

        .hs_int_start_stop_x                    = 0x001E0322,

        .hs_ext_start_stop_x                    = 0x000F0359,
        .vs_int_start_x                         = 0x01A00000,
        .vs_int_stop_x__vs_int_start_y          = 0x020701A0,
        .vs_int_stop_y__vs_ext_start_x          = 0x01AC0024,
        .vs_ext_stop_x__vs_ext_start_y          = 0x020D01AC,
        .vs_ext_stop_y                          = 0x00000006,
        .avid_start_stop_x                      = 0x03480078,
        .avid_start_stop_y                      = 0x02060024,
        .fid_int_start_x__fid_int_start_y       = 0x0001008A,
        .fid_int_offset_y__fid_ext_start_x      = 0x01AC0106,
        .fid_ext_start_y__fid_ext_offset_y      = 0x01060006,
        .tvdetgp_int_start_stop_x               = 0x00140001,
        .tvdetgp_int_start_stop_y               = 0x00010001,
        .gen_ctrl                               = 0x00FF0000,
        .width = 640,
        .height = 482

 

 

regards,

Sairam.S

  • 0
    TI__Mastermind 43875 points

    Sairam,

    You cannot change the timing parameters for the NTSC signal. The NTSC standard determines what they MUST be.

    If your source image is 640x482 then you can either offset the image on the display by (720-640)/2 = 40, or scale the image up to 720 wide.

    I recommend adding an image shift since all TVs will perform what is called overscan, which has the effect of making the outer 10% or so of the image not visible (falls off the edge of the screen so to speak), so by displaying 640 pixels offset on the 720 wide display means that your image will be entirely displayed (horizontally at least).

    What you really need to do is configure the display sub-system and not the VENC.

    I am not sure if there is a simple way to do this "correctly" through the OS, but the hardware is capable.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 150 points

    Hi Steve ,

     

    I tried modifying the registers DISPC_GFX_POSITION . But  my image of 640x482 did not  get fit in this .It is not even moving even i tried giving extreme values .

     

    Kindly provide some code snippets at the boot loader level which can make my life easier so as to display 640x482 image in NTSC mode on a CRT television.

     

    regards ,

    Sairam.S

  • 0 in reply to sairam
    Expert 1400 points

    hi steve,

    we r able to get the DM3730 display on TV using its TVOUT signals... but TVOUT signal stops coming if the LCD resolution is greater then 800*600....so what might be the problem???

    we want to use the TV out @ 1024*768 resolution since our LCD panel resolution is 1024*768..... and we want to display on  both tvout n lcd 

    thnx u in advance ......

  • 0 in reply to suhas_m
    Expert 1400 points

    hi Steve, here is my DSS register dump......for 1024*600 resolution..... but no signal on tv..tv is blank...

    DSS Registers:
    DSS_REVISIONNUMBER=0x00000020
    DSS_SYSCONFIG=0x00000001
    DSS_SYSSTATUS=0x00000001
    DSS_CONTROL=0x00000038
    DSS_SDI_CONTROL=0x00000000
    DSS_PLL_CONTROL=0x00000000
    DSS_SDI_STATUS=0x00000081
     
    DISPC Registers:
    DISPC_REVISION=0x00000030
    DISPC_SYSCONFIG=0x00001009
    DISPC_SYSSTATUS=0x00000001
    DISPC_IRQSTATUS=0x000081AE
    DISPC_IRQENABLE=0x00005240
     
    DISPC Registers (Control):
    DISPC_CONTROL=0x0801830B
    DISPC_CONFIG=0x00000208
    DISPC_CAPABLE=0x000003FF
    DISPC_DEFAULT_COLOR0=0x00000000
    DISPC_DEFAULT_COLOR1=0x00000000
    DISPC_TRANS_COLOR0=0x00000000
    DISPC_TRANS_COLOR1=0x00000000
    DISPC_GLOBAL_ALPHA=0x00FF00FF
     
    DISPC Registers (LCD):
    DISPC_LINE_STATUS=0x0000013B
    DISPC_LINE_NUMBER=0x00000000
    DISPC_TIMING_H=0x0780C801
    DISPC_TIMING_V=0x00F01400
    DISPC_POL_FREQ=0x00023000
    DISPC_DIVISOR=0x00010001
    DISPC_SIZE_DIG=0x012002CF
    DISPC_SIZE_LCD=0x025703FF
     
    DISPC Registers (GFX):
    DISPC_GFX_BA0=0x82802000
    DISPC_GFX_BA1=0x82802000
    DISPC_GFX_POSITION=0x00000000
    DISPC_GFX_SIZE=0x025703FF
    DISPC_GFX_ATTRIBUTES=0x000000AD
    DISPC_GFX_FIFO_THRESHOLD=0x03FF01FF
    DISPC_GFX_FIFO_SIZE_STATUS=0x00000400
    DISPC_GFX_ROW_INC=0x00000001
    DISPC_GFX_PIXEL_INC=0x00000001
    DISPC_GFX_WINDOW_SKIP=0x00000000
    DISPC_GFX_TABLE_BA=0x89A62000
     
    DISPC Registers (VID 1):
    BA0=0x00000000
    BA1=0x00000000
    POSITION=0x00000000
    SIZE=0x00000000
    ATTRIBUTES=0x00000000
    FIFO_THRESHOLD=0x03FF03C0
    FIFO_SIZE_STATUS=0x00000400
    ROW_INC=0x00000001
    PIXEL_INC=0x00000001
    FIR=0x00000000
    PICTURE_SIZE=0x00000000
    ACCU0=0x00000000
    ACCU1=0x00000000
    DISPC_VIDn_FIR_COEF_Hi _HVi _Vi:
       0: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       1: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       2: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       3: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       4: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       5: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       6: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       7: H = 0x00000000   HV = 0x00000000   V = 0x00000000
    CONV_COEF0=0x00000000
    CONV_COEF1=0x00000000
    CONV_COEF2=0x00000000
    CONV_COEF3=0x00000000
    CONV_COEF4=0x00000000
     
    DISPC Registers (VID 2):
    BA0=0x82802800
    BA1=0x82802000
    POSITION=0x002A002C
    SIZE=0x00C90287
    ATTRIBUTES=0x006183ED
    FIFO_THRESHOLD=0x03FF01FF
    FIFO_SIZE_STATUS=0x00000400
    ROW_INC=0x00000001
    PIXEL_INC=0x00000001
    FIR=0x0BE10652
    PICTURE_SIZE=0x025703FF
    ACCU0=0x01F00000
    ACCU1=0x00000000
    DISPC_VIDn_FIR_COEF_Hi _HVi _Vi:
       0: H = 0x1b761bea   HV = 0x243624ea   V = 0x00000101
       1: H = 0x2b730dee   HV = 0x28371fe7   V = 0x000004fe
       2: H = 0x3a6b00f4   HV = 0x2c361be7   V = 0x000008fb
       3: H = 0x475ff6fa   HV = 0x303516ea   V = 0x00000df8
       4: H = 0xef5151ef   HV = 0x12333300   V = 0x0000f612
       5: H = 0xf65f47ea   HV = 0x163530fa   V = 0x0000f80d
       6: H = 0x006b3ae7   HV = 0x1b362cf4   V = 0x0000fb08
       7: H = 0x0d732be7   HV = 0x1f3728ee   V = 0x0000fe04
    CONV_COEF0=0x0199012A
    CONV_COEF1=0x012A0000
    CONV_COEF2=0x079C0730
    CONV_COEF3=0x0000012A
    CONV_COEF4=0x00000205

  • 0 in reply to suhas_m
    Expert 1400 points

    hi Steve....

    i thought it will be helpful if i post a register dump for 800*600 resolution..... with 800*600 resolution my tv out signal is coming... im able display on tv... below is the tested n working register dump for 800*600 resolution....... pls try to compare both....and suggest me a solution...

    DSS Registers:
    DSS_REVISIONNUMBER=0x00000020
    DSS_SYSCONFIG=0x00000001
    DSS_SYSSTATUS=0x00000001
    DSS_CONTROL=0x00000038
    DSS_SDI_CONTROL=0x00000000
    DSS_PLL_CONTROL=0x00000000
    DSS_SDI_STATUS=0x00000081
     
    DISPC Registers:
    DISPC_REVISION=0x00000030
    DISPC_SYSCONFIG=0x00001009
    DISPC_SYSSTATUS=0x00000001
    DISPC_IRQSTATUS=0x0000A1AE
    DISPC_IRQENABLE=0x00005240
     
    DISPC Registers (Control):
    DISPC_CONTROL=0x0801830B
    DISPC_CONFIG=0x00000208
    DISPC_CAPABLE=0x000003FF
    DISPC_DEFAULT_COLOR0=0x00000000
    DISPC_DEFAULT_COLOR1=0x00000000
    DISPC_TRANS_COLOR0=0x00000000
    DISPC_TRANS_COLOR1=0x00000000
    DISPC_GLOBAL_ALPHA=0x00FF00FF
     
    DISPC Registers (LCD):
    DISPC_LINE_STATUS=0x0000014F
    DISPC_LINE_NUMBER=0x00000000
    DISPC_TIMING_H=0x0970273F
    DISPC_TIMING_V=0x01700103
    DISPC_POL_FREQ=0x00020000
    DISPC_DIVISOR=0x00010002
    DISPC_SIZE_DIG=0x012002CF
    DISPC_SIZE_LCD=0x0257031F
     
    DISPC Registers (GFX):
    DISPC_GFX_BA0=0x82802000
    DISPC_GFX_BA1=0x82802000
    DISPC_GFX_POSITION=0x00000000
    DISPC_GFX_SIZE=0x0257031F
    DISPC_GFX_ATTRIBUTES=0x000000AD
    DISPC_GFX_FIFO_THRESHOLD=0x03FF01FF
    DISPC_GFX_FIFO_SIZE_STATUS=0x00000400
    DISPC_GFX_ROW_INC=0x00000001
    DISPC_GFX_PIXEL_INC=0x00000001
    DISPC_GFX_WINDOW_SKIP=0x00000000
    DISPC_GFX_TABLE_BA=0x89A86000
     
    DISPC Registers (VID 1):
    BA0=0x00000000
    BA1=0x00000000
    POSITION=0x00000000
    SIZE=0x00000000
    ATTRIBUTES=0x00000000
    FIFO_THRESHOLD=0x03FF03C0
    FIFO_SIZE_STATUS=0x00000400
    ROW_INC=0x00000001
    PIXEL_INC=0x00000001
    FIR=0x00000000
    PICTURE_SIZE=0x00000000
    ACCU0=0x00000000
    ACCU1=0x00000000
    DISPC_VIDn_FIR_COEF_Hi _HVi _Vi:
       0: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       1: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       2: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       3: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       4: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       5: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       6: H = 0x00000000   HV = 0x00000000   V = 0x00000000
       7: H = 0x00000000   HV = 0x00000000   V = 0x00000000
    CONV_COEF0=0x00000000
    CONV_COEF1=0x00000000
    CONV_COEF2=0x00000000
    CONV_COEF3=0x00000000
    CONV_COEF4=0x00000000
     
    DISPC Registers (VID 2):
    BA0=0x82802640
    BA1=0x82802000
    POSITION=0x000E002C
    SIZE=0x01020287
    ATTRIBUTES=0x006183ED
    FIFO_THRESHOLD=0x03FF01FF
    FIFO_SIZE_STATUS=0x00000400
    ROW_INC=0x00000001
    PIXEL_INC=0x00000001
    FIR=0x094404F0
    PICTURE_SIZE=0x0257031F
    ACCU0=0x00A20000
    ACCU1=0x00000000
    DISPC_VIDn_FIR_COEF_Hi _HVi _Vi:
       0: H = 0x028002fe   HV = 0x264c26fe   V = 0x0000f4f4
       1: H = 0x147df405   HV = 0x2f481ff6   V = 0x0000f8f2
       2: H = 0x2974ea0b   HV = 0x354916ee   V = 0x0000fcf0
       3: H = 0x3e66e50f   HV = 0x3b450fe8   V = 0x000001f0
       4: H = 0xe45353e4   HV = 0x08404012   V = 0x0000f008
       5: H = 0xe5663ee8   HV = 0x0f453b0f   V = 0x0000f001
       6: H = 0xea7429ee   HV = 0x1649350b   V = 0x0000f0fc
       7: H = 0xf47d14f6   HV = 0x1f482f05   V = 0x0000f3f7
    CONV_COEF0=0x0199012A
    CONV_COEF1=0x012A0000
    CONV_COEF2=0x079C0730
    CONV_COEF3=0x0000012A
    CONV_COEF4=0x00000205