• State TI Thinks Resolved
  • Locked Locked
  • Replies 12 replies
  • Answers 3 answers
  • Subscribers 100 subscribers
  • Views 2258 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

J6 Processor SDK Linux: Power management configuration part of release or create own?

John H. Gardner
Guru 51641 points
Other Parts Discussed in Thread: DRA742, DRA72


Current understanding is that he PMIC first turns on and performs the Power on sequence with the voltage values configured according to the OTP used. Once the J6 boots up, it changes the various PMIC voltages according to its own programmed AVS settings.

Question - Is this configuration of the PMIC, already implemented as part of the GLSDK ? Or should a customer explicitly implement this in the application that they develop on the GLSDK ?

  • 0
    TI__Guru**** 161600 points
    Hi John,

    This is already been implemented in GLSDK to some extent (see release nots & GLSDK datasheet for info). It is also possible to alter PMIC voltages with AVS, according to what the PRCM supports (NOTE that you need to be very well familiar with DRA7xx PRCM). However, this is quite time consuming modification of the power management architecture of the linux kernel ...

    Relevant files are:
    - defconfig: you should make sure the avs support is enabled
    CONFIG_POWER_AVS=y
    CONFIG_VOLTAGE_DOMAIN=y

    - appropriate opp configurations in the dts or arch/arm/mach-map2/opp7xx_data.c (depending on your kernel version) may be required.
    - also in have a look at arch/arm/mach-map2/ files for possible SoC related modifications.
    - on PMIC side you need to look at the sources in:
    drivers/mfd/ (see the driver of your PMIC)
    drivers/regulator/ti-abb-regulator.c & the corresponding PMIC regulator.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 70 points
    Dear Yordan,

    I has enable some setting in kernel config
    CONFIG_POWER_AVS=y
    CONFIG_VOLTAGE_DOMAIN=y
    CONFIG_SOC_DRA7XX=y ( “arch/arm/mach-omap2/opp7xx_data.c” )
    CONFIG_MFD_PALMAS=y ( "driver/mfd/palmas.c” ) ( for TPS659038 and TPS65917)
    CONFIG_REGULATOR_TI_ABB=y ( “drivers/regulator/ti-abb-regulator.c” )
    CONFIG_REGULATOR_PALMAS=y ( “drivers/regulator/palmas-regulator.c” ) ( for TPS659038 and TPS65917)

    But there are some problems about smartreflex/voltage domain/PMIC on my system.
    Would you help to provide your comment for the problem. It is seem the AVS doesn't work.

    ---------------------------------------------------------------------------------------------------

    Starting kernel ...

    [ 0.000000] Booting Linux on physical CPU 0x0
    [ 0.000000] Linux version 3.14.63 (jonathan@jonathan-TravelMate-P245-M) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #10 SMP PREEMPT Tue Aug 23 15:08:41 UTC 2016
    [ 0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
    [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [ 0.000000] Machine model: TI DRA742
    ...
    [ 3.961371] sr_init: No PMIC hook to init smartreflex
    [ 3.966770] sr_init: platform driver register failed for SR
    ...
    [ 8.302847] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.voltdm
    [ 8.302851] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.voltdm
    [ 8.302879] omap_voltdm 4a003b20.voltdm: Unable to get vdd regulator:-517
    [ 8.302888] cpu cpu0: of_pm_voltdm_notifier_register: Failed to get cpu0 regulator/voltdm: -517
    [ 8.302893] cpu cpu0: cpu0 clock notifier not ready, retry
    [ 8.302909] platform cpufreq-cpu0.0: Driver cpufreq-cpu0 requests probe deferral
    ...
    [ 8.367972] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.voltdm
    [ 8.367976] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.voltdm
    [ 8.367999] omap_voltdm 4a003b20.voltdm: Unable to get vdd regulator:-517
    [ 8.368006] cpu cpu0: of_pm_voltdm_notifier_register: Failed to get cpu0 regulator/voltdm: -517
    [ 8.368011] cpu cpu0: cpu0 clock notifier not ready, retry
    [ 8.368025] platform cpufreq-cpu0.0: Driver cpufreq-cpu0 requests probe deferral

    Best regards,
    Jonathan
  • 0 in reply to Jonathan Pan
    TI__Guru**** 161600 points
    Hi Jonathan,

    I tested this on my J6Eco EVM, running GLSDK7.04.00.03 (kernel 3.14.63), and I didn't see the bellow problems:
    sr_init: No PMIC hook to init smartreflex
    sr_init: platform driver register failed for SR
    ....
    [ 8.302847] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.voltdm
    [ 8.302851] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.voltdm
    [ 8.302879] omap_voltdm 4a003b20.voltdm: Unable to get vdd regulator:-517

    Can you share which PMIC are you using? Also is it possible to attach your dts & dtsi files (the request probe deferral errors indicate problems with the dts nodes (or platform related sources in arch/arm/mach-omap2)?

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 70 points

    Dear Yordan, 

    PMIC is TPS659039.  MCU is TI DRA742,

    The dts & dtsi files are also attached. 

    Do you know what to check AVS/smartreflex driver is work on your J6Eco EVM,

    Is it possible to check AVS/smartreflex on debugfs ?

    dra7_dts.zip

  • 0 in reply to Jonathan Pan
    TI__Expert 4230 points
    Hi folks,
    The AVS algorithm used on DRA7x is different from earlier OMAP3/DM81x platforms.
    It does not use SmartReflex3 so you'll see following prints, if the SmartReflex driver is enabled but it can safely be ignored.
    sr_init: No PMIC hook to init smartreflex
    sr_init: platform driver register failed for SR

    The AVS used on DRA7x is called AVS class 0.
    Which means the optimal voltage values for each silicon for each VDD and per OPP are already stored in efuse.
    Both U-boot and Kernel have appropriate hooks in place to read the efuses and configure the optimized voltages as per the OPP.

    Customer doesn't need to worry about configuring the AVS voltages.

    Note that this is independent of PMIC under use as long as the regulator driver is implemented as expected by the framework

    To check if the optimised voltages are successfully programmed or not one can measure the voltage of each VDD before loading MLO and after.



    Regards,
    RK
  • 0 in reply to Jonathan Pan
    TI__Expert 6256 points

    Jonathan,

    We are using TPS65917 on J6eco(DRA72x).

    is your question on J6eco ? or J6x(DRA74x)?

    Have you looked at uboot changes for j6eco:

    git.omapzoom.org/

  • 0 in reply to Praneeth Bajjuri
    TI__Expert 6256 points
    Hi Jonathan,

    TI EVMs are

    Please review few things.
    1.
    Ensure you have all the changes from current GLSDK7.x release in your code base.
    uboot:
    arch / arm / include / asm / arch-omap5 / clock.h
    arch/arm/cpu/armv7/omap5/hw_data.c
    arch/arm/cpu/armv7/omap-common/clocks-common.c
    arch/arm/include/asm/arch-omap4/sys_proto.h
    arch/arm/include/asm/arch-omap5/sys_proto.h
    arch/arm/include/asm/omap_common.h

    2.
    TI DRA72 EVM uses TPS65917
    TI DRA74/5 EVM uses TPS6590x

    3.
    AVS class 0 is supported.. please use omapconf to review sr/avs functionality.

    Take latest version: github.com/.../releases
    Usage: github.com/.../wiki

    Share the omapconf sr , and dpll log
  • 0 in reply to Praneeth Bajjuri
    Prodigy 70 points

    Hi Praneeth,


    I have the question on both J6eco and J6x.

    For item1, I will check those files.

    For item2, J6eco(DRA72x) has TPS65917, J6x(DRA74x) has TPS659039.

    For item3, yes, I can see AVS via omapconf command.

    But I also check the PMIC SMPS voltage, some SMPS's voltage value is not same with efuse value of normal, over-drive or high performance.


    Jonathan

  • 0 in reply to Jonathan Pan
    TI__Expert 4230 points


    Jonathan,

    >>>But I also check the PMIC SMPS voltage, some SMPS's voltage value is not same with efuse value of normal, over-drive or high performance.

    How are you measuring and comparing the voltages?

    Can you give details of the VDD rails for which you see the voltage mismatch?

    Regards,

    RK

  • 0 in reply to Ravikumar Kattekola
    Prodigy 70 points

    Dear Ravikumar,


    The AVS value is below on J6x (DRA74x)

    AVS-VDD_MPU
        OPP_NOM 975, OPP_OD 1063,  OPP_HIGH 1224

    AVS-VDD_DSPEVE
        OPP_NOM 965, OPP_OD 1020,  OPP_HIGH 1050

    AVS-VDD_GPU
        OPP_NOM 1020, OPP_OD 1040,  OPP_HIGH 1050

    AVS-VDD
        OPP_NOM 1020,

    AVS-VDD_IVA
        OPP_NOM 970, OPP_OD 1010,  OPP_HIGH 1075


    I measure SMPS voltage as below, the voltage is same with PMIC register setting for SMPS voltage..

    (VDD_MPU) SMPS12 980 mV     -- is close to AVS OPP-NOM
    (VDD_DSPEVE) SMPS45 1020 mV     -- is differ with AVS OPP-NOM
    (VDD_GPU) SMPS6 1050 mV      -- is differ with AVS OPP-NOM
    (VDD) SMPS7 1020 mV      -- is same with AVS OPP-NOM
    (VDD_IVA) SMPS8 1080 mV     -- is differ to AVS OPP-NOM

    It is seem some SMPS(DSPEVE, GPU and IVA) voltage aren't same with OPP-NOM mode value. Is it work correctly ?

    Best regards,
    Jonathan

  • 0 in reply to Ravikumar Kattekola
    Prodigy 70 points
    Dear Ravikumar,

    The AVS value is below on J6x (DRA74x)
    AVS-VDD_MPU
    OPP_NOM 975, OPP_OD 1063, OPP_HIGH 1224

    AVS-VDD_DSPEVE
    OPP_NOM 965, OPP_OD 1020, OPP_HIGH 1050

    AVS-VDD_GPU
    OPP_NOM 1020, OPP_OD 1040, OPP_HIGH 1050

    AVS-VDD
    OPP_NOM 1020,

    AVS-VDD_IVA
    OPP_NOM 970, OPP_OD 1010, OPP_HIGH 1075

    I measure SMPS voltage as below, the voltage is same with PMIC register setting for SMPS voltage..
    (VDD_MPU) SMPS12 980 mV -- close to 975 (AVS OPP-NOM)
    (VDD_DSPEVE) SMPS45 1020 mV -- differ with 965 (AVS OPP-NOM)
    (VDD_GPU) SMPS6 1050 mV -- differ with 1020 (AVS OPP-NOM)
    (VDD) SMPS7 1020 mV -- same with 1020 (AVS OPP-NOM)
    (VDD_IVA) SMPS8 1080 mV -- differ with 970 (AVS OPP-NOM)

    It is seem some SMPS(DSPEVE, GPU and IVA) voltage aren't same with OPP-NOM mode value. Is it work correctly ?

    Best regards,
    Jonathan
  • 0 in reply to Jonathan Pan
    TI__Expert 4230 points

    Hi jonathan,

    If you are using GLSDK 7.04, then IVA is by default running at OPP_HIGH not OPP_NOM that's why you see higher voltage on VDD_IVA

    Same with  DSPEVE, DSP is not at OPP_NOM but it's at OPP_OD hence higher voltage and VDD_DSPEVE.

    There's nothing to worry, it's as expected. 

    You can check this in dra74x.dtsi, you'll find iva_coproc and dsp_coproc nodes. clock-target-frequency field tells what's the frequency configured at boot up.

    GPU is also configured to run at higher frequency and voltage in U-boot.

    You may check OPP info (freq and voltage) by running "omapconf show opp" at kernel prompt.

    Regards,

    RK