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AM335x ICEv2 issue with IGH EtherCAT Master for Linux

jason lee94
Prodigy 90 points
Other Parts Discussed in Thread: AM3359, AM3357, SYSBIOS

hi, all

i am install igh ethercat master for linux 1.5.2 on my beagbone black with xenomai real-time operating system.

now two ethercat slaves were link with my BBB, and one is 3359 icev2(asysbios_ind_sdk_02.01.02.02),another is xmc4800(infineon).

when i insmod ec_master.ko & ec_generic.ko , now two slaves will go to PREOP state.

here is more infomation:
root@beaglebone:bin#./ethercat slave
0 0:0 PREOP + XMC4800_Relax_Generic_EtherCat_Slave
1 0:1 PREOP + AM3357/AM3359 (PRU-ICSS v1.0

when i run my application, DC Slave mode is configured at master (IgH) and xmc4800 is reference slave.

goes wrong while going to OP state ：

ethercat master display some errors on terminal,for example
[ 2116.441292] EtherCAT ERROR 0: Failed to receive delay measuring datagram on main link: Datagram timed out.
[ 2116.693289] EtherCAT ERROR 0: Failed to receive address clearing datagram on main link: Datagram timed out.

and, when i execute command "./ethercat slave' ,nothing i can get.
root@beaglebone:bin#./ethercat slave
root@beaglebone:bin#

and ,now two slaves still in PREOP state.
so ,what should i do.

note:

3359 slave work well when the ethercat master is TwinCAT.

when 3359 is not on ethertcat slave bus ,IGH work well.

  • 0
    TI__Guru**** 393215 points
    Hi,

    I have notified the EtherCAT experts. They will respond here.
  • 0
    Prodigy 90 points

    i got some infomations in EtherCAT_ISDK_01_01_01_Errata.pdf 

    page 20:

    Rx Time Port1 (0x904) time stamping not done correctly when write to 0x900 is done cyclically

    • Issue/ Failure Description or state

    – SDOCM00108541: Rx Time Port1 (0x904) time stamping is missed when write (BWR) to 0x900 is done cyclically

    • Conditions in which failures occur

    – When EtherCAT master cyclically write to 0x900 register and two ports of EtherCAT slave is active or randomly for first write 0x900 after a link up event

    • Root cause

    – Parsing algorithm was not scheduled on time due to cycle budget crunch in firmware and this resulted in RX L2 FIFO overflow and parsing errors

    – Parsing algorithm and firmware optimizations were done to fix overflow

    – Parsing algorithm had a bug : which missed to detect write to 0x900 when datagram address (ado) word is split into two banks of L2 FIFO as separate bytes

    but,Then how should I begin.

    jason

  • 0 in reply to Biser Gatchev-XID
    TI__Expert 5116 points
    Hi Biser,
    Is there any update on this issue?
    More customers get the similar issue and still not be solved.
    Thanks!
    Thomas
  • 0 in reply to Thomas Yang55737
    Prodigy 200 points
    Hi, all.
    I has encountered the similar problem.

    ethercat master: Beaglebone black, IGH1.5.2, Linux+xenomai;
    ethercat slave: ICE3359v2, SDK2.1.2.2;

    project:C:\ti\sysbios_ind_sdk_02.01.02.02\sdk\protocols\ethercat_slave\ecat_appl


    IGH1.5.2 could connect two servos from different corporations, and make them working on CSP or CSV mode.

    However, IGH1.5.2 could not change ICE3359v2 to OP state.

    when I use wireshark to capture datagram from ICE3359v2, I found there is no response datagrams in SafeOP state, but could get AlStatus datagrams in PreOP state.

    Addition Mentions: The TI_LED project works wells(TIESC_APPLICATION=1,CiA402_Device=0), but the CiA402 project(TIESC_APPLICATION=0,CiA402_Device=1) does cause the problem above.

    why?

    Thanks.
  • 0 in reply to Lyu Frank
    TI__Expert 7570 points
    Hi

    We were able to run IGH master with AM3 EtherCAT slave in CIA402 mode using the latestSYSBIOSSDK-IND-SITARA: SYSBIOS Industrial Software Development Kit (SDK) for AM335x and AM437x release.

    The slaves go to OP state.
    Would it be possible to share the logs?

    David
  • 0 in reply to David Zaucha
    Prodigy 200 points

    Dear David,

    I have updated SDK to the latest SYSBIOSSDK-IND-SITARA(Version 02_01_03_02) for AM335x release.
    Only two steps were done as follows:

    Step1:
    Apply TI_ECAT.patch file on SSC_V5i11 stack code, and copy the patched files(.c and .h) to C:\ti\sysbios_ind_sdk_02.01.03.02\sdk\protocols\ethercat_slave\ecat_appl\EcatStack\.
    Step2:
    Modify the macro value of TIESC_APPLICATION from 1 to 0, CiA402_DEVICE from 0 to 1.

    The critical error shows "The EtherCAT ERROR 0-0: Failed to receive state checking datagram: Datagram timed out".

    Here are my questions:

    Why ICE3359v2 could not send datagram of  AlStatus(SafeOP state) to IGH1.5.2 Master?

    Are there any other steps that need to be done for ecat_appl project?


    Thank you for all your assistance.

    Frank



    The logs of CiA402 ecat_appl project are attached below.

    ----------------------------------------------------------------------------------------------------
    [ 4992.282671] libphy: 4a101000.mdio:00 - Link is Up - 100/Full
    [ 4992.288640] EtherCAT 0: Link state of ecm0 changed to UP.
    [ 4992.298355] EtherCAT 0: 1 slave(s) responding on main device.
    [ 4992.304409] EtherCAT 0: Slave states on main device: INIT.
    [ 4992.318426] EtherCAT 0: Scanning bus.
    [ 4993.209923] EtherCAT 0: Bus scanning completed in 900 ms.
    [ 4993.215599] EtherCAT 0: Using slave 0 as DC reference clock.
    [ 4993.221536] EtherCAT ERROR 0: Failed to calculate bus topology.
    [ 4993.231779] EtherCAT 0: Slave states on main device: PREOP.
    [ 4999.570711] EtherCAT: Requesting master 0...
    [ 4999.575303] EtherCAT: Successfully requested master 0.
    [ 4999.584474] EtherCAT 0: Domain0: Logical address 0x00000000, 12 byte, expected working counter 3.
    [ 4999.593862] EtherCAT 0: Datagram domain0-0-main: Logical offset 0x00000000, 12 byte, type LRW.
    [ 4999.607114] EtherCAT 0: Master thread exited.
    [ 4999.611951] EtherCAT 0: Starting EtherCAT-OP thread.
    [ 4999.619687] EtherCAT WARNING 0: 147 datagrams TIMED OUT!
    [ 4999.625594] EtherCAT WARNING 0: No app_time received up to now, but master already active.
    [ 4999.704126] EtherCAT 0: Domain 0: Working counter changed to 3/3.
    [ 4999.734619] EtherCAT ERROR 0-0: Failed to receive state checking datagram: Datagram timed out.
    [ 4999.749789] EtherCAT 0: 0 slave(s) responding on main device.
    [ 5000.618145] EtherCAT WARNING 0: 166 datagrams TIMED OUT!
    [ 5000.624145] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 905 times.
    [ 5000.707110] EtherCAT 0: Domain 0: Working counter changed to 0/3.
    [ 5001.619144] EtherCAT WARNING 0: 184 datagrams TIMED OUT!
    [ 5001.627128] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 985 times.
    [ 5002.619141] EtherCAT WARNING 0: 181 datagrams TIMED OUT!
    [ 5002.629121] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 987 times.
    [ 5003.619142] EtherCAT WARNING 0: 182 datagrams TIMED OUT!
    [ 5003.631123] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 987 times.
    [ 5004.619140] EtherCAT WARNING 0: 184 datagrams TIMED OUT!
    [ 5004.633121] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 984 times.
    [ 5005.619146] EtherCAT WARNING 0: 179 datagrams TIMED OUT!
    [ 5005.634128] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 987 times.
    [ 5006.618140] EtherCAT WARNING 0: 184 datagrams TIMED OUT!
    [ 5006.636122] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 984 times.
    [ 5007.618140] EtherCAT WARNING 0: 183 datagrams TIMED OUT!
    [ 5007.638121] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 986 times.
    [ 5008.619142] EtherCAT WARNING 0: 184 datagrams TIMED OUT!
    [ 5008.641120] EtherCAT WARNING: Datagram df47b14c (domain0-0-main) was SKIPPED 987 times.
    [ 5009.033006] EtherCAT 0: Releasing master...
    [ 5009.038827] EtherCAT 0: Master thread exited.
    [ 5009.043928] EtherCAT 0: Starting EtherCAT-IDLE thread.
    [ 5009.049764] EtherCAT 0: Released.
    [ 5009.057745] EtherCAT 0: 1 slave(s) responding on main device.
    [ 5009.063800] EtherCAT 0: Slave states on main device: SAFEOP.
    [ 5009.077977] EtherCAT 0: Scanning bus.
    [ 5009.945719] EtherCAT 0: Bus scanning completed in 875 ms.
    [ 5009.951420] EtherCAT 0: Using slave 0 as DC reference clock.
    [ 5009.957361] EtherCAT ERROR 0: Failed to calculate bus topology.
    [ 5010.007743] EtherCAT 0: Slave states on main device: PREOP.

  • 0 in reply to Lyu Frank
    TI__Expert 7570 points

    Hi Frank

    In addition to modifying the TI_ESC application it is necessary to also modify the IGH master (main.c) code.

    With the below mentioned steps we were able to get the boards to OP state in cia402 mode on IGH master.

    Step 1: The boards have to be flashed with the EEPROM of cia402.

    Step 2: The correct PDO entries have to be copied to the main.c file of IGH master.
    sudo ethercat cstruct -> is the command to get the PDO entries.
    The result of the above command will be different for TIESC_APPLICATION and CiA402_DEVICE

    Step 3: The function call, "ecrt_slave_config_reg_pdo_entry" in main.c file of IGH master has to be modified with the obtained addresses from the step 2 command.

    Step 4: Compile the master code.
    make

    David

  • 0 in reply to David Zaucha
    Prodigy 200 points

    Hi,David
    Thank you for your detailed reply.

    Step2~Step4 has been done before. Step1 was forgotten.
    How to finish step1? Use twincat or modify cia402 source code?

    In twincat, I see there is a option to download eeprom, which is located at IO/Devices/Device3/Box1/EtherCAT/Advanced Settings/EEPROM/Hex Editor.

    Frank

  • 0 in reply to David Zaucha
    Prodigy 200 points
    Hi,David,
    I am sorry to response so late.
    According to your advices, ICE3359 has run in CiA402 mode and communicated with IGH1.5.2.

    Best regards,

    Frank Lyu
  • 0 in reply to Lyu Frank
    TI__Expert 7570 points
    Frank

    Thank you.

    David