I checked the related threads:
https://e2e.ti.com/support/arm/sitara_arm/f/791/t/359417
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/198104/1637664#1637664
Spread spectrum clocking (SSC) is supported on output clocks of the on-chip DPLLs, but it is not supported for DDR, PER, DISP, and CORE PLLs.
An LVCMOS square-wave digital clock source with SSC can be connected to OSC0, but it seems to be very difficult to meet the reference clock requirements for OSC0.
In BeagleBone Green, OSC0 is connected to SSCG. I cannot clear whether this SSCG meets the reference clock requirements for OSC0.
http://www.seeedstudio.com/wiki/File:BEAGLEBONE_GREEN_V1.pdf
Our customer designs the medical equipment. It is required to reduce EMI.
Please tell me the better solution to reduce EMI in clocking.
Best regards,
Daisuke
