SDRAM data failures on C6713

Hi Lloyd,

I can suggest you two options.

Option 1:

==========

Using the CCS gel file( dskC6713.gel ) , go to the SDRAM configuration section like, init_emif(), modify it according to your custom board and the SDRAM chip.

Use the below PSEUDO code  to do a simple read / write test in the gel file itself. Give the  appropriate Base address of the SDRAM.

hotmenu SDRAM_write_read_test()
{
//int data_set[4];
    //= {0xAAAAAAAA, 0x55555555, 0xFFFFFFFF, 0x00000000};
    unsigned int write_data = 0xAAAAAAAA;
    unsigned int read_data = 0x0;
    unsigned int errors = 0;
    int dw;
    unsigned int i, mem_start, mem_size, mem_location;
    mem_start = SDRAM_BASE_ADDRESS + (DNUM * 0x01000000);
    mem_size = 0x100;
    for(dw=0;dw<4;dw++)
    {
        if (dw == 0) write_data = 0xAAAAAAAA;
        if (dw == 1) write_data = 0x55555555;
        if (dw == 2) write_data = 0xFFFFFFFF;
        if (dw == 3) write_data = 0x00000000;
        mem_location = mem_start;
        GEL_TextOut( "Memory Test Write Core: %d, Mem Start: 0x%x, Mem Size: 0x%x, value: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size,write_data);
        for(i=0;i<mem_size;i++)
        {
            *( unsigned int* )(mem_location) = write_data;
            mem_location += 4;
        }
        mem_location = mem_start;
        GEL_TextOut( "Memory Test Read Core: %d, Mem Start: 0x%x, Mem Size: 0x%x ...\n",,2,,,DNUM,mem_start,mem_size);
        for (i=0;i<mem_size;i++)
        {
            read_data = *( unsigned int* )(mem_location);
            if (read_data != write_data)
            {
                GEL_TextOut("SDRAM Data Error: DSP Core: %d, Mem Addr: 0x%x, read: 0x%x, expected: 0x%x \n",,2,,,DNUM,(SDRAM_BASE_ADDRESS + (i * 4)),read_data,write_data);
                errors++;
            }
            mem_location += 4;
        }
        if (errors == 0)
        {
            GEL_TextOut( "Memory Test Done, no errors found.\n" );
        }
        else
        {
            GEL_TextOut("Memory Test Done, %d errors were encounterd. \n",,2,,,errors);
        }
    }
    GEL_TextOut( "All Memory Test Completed on core: %d with %d errors.\n",,2,,,DNUM,errors);

}

Option 2:

=======

If you have configured all the parameters of EMIF and SDRAM, you can use the CCS Memory browser and do a read write directly into the memory mapped addresses of SDRAM.

The window will show something like below.

Lloyd,

Are the memory errors consistent between boards? Are they consistent on a single board, meaning the same location will read with the same bit set or cleared every time?

Can you establish whether it is an apparent write error (always read the same wrong value after a write, but it might change the next time you write to that location) or an apparent read error (different values read from the same location)?

Without knowing more details, it is difficult to predict a failure, but I will say (not just because I work at TI) that you should consider the SDRAM being at fault, too, especially if this is a new batch of boards and only two are failing out of several. We have not made any revisions to the C6713 design in many years, and its test program is the same that it has been for many years.

When you are changing the timing parameters, add an extra cycle to all of the timing parameters including things like transition delays before and after refresh. Some may need a cycle removed to make it more relaxed, but I cannot think of an example right now.

Another thing you can try to isolate the problem is to spray cold-spray on the SDRAM and see if the problem persists, then spray the DSP and see if the problem persists. The cold-spray will make the devices run faster, usually. You could try the same thing with a heat gun to make them run slower.

Regards,
RandyP

Shankari,

Thanks for replying. We have good memory diagnostics, I was hoping to find guidance on any known bugs or tricks in the dram controller area.

Lloyd

RandyP,

Thanks for your suggestions.

I have a lot of experience with DRAMs and this problem looks difficult. These are old boards that never had the DRAM tested, and now we want to use that memory. The errors are not repeatable or consistent (different addresses each time, different incorrect data at each location). For now I only have 2 boards to work with. They both fail all the SDRAM diagnostics most of the time and all the other diagnostics on external mem (SRAM and FLASH) pass all the time.

The failures seem to indicate both bad writing and bad reading. I've tried setting Trcd and Trp much looser than required (9 clocks long instead of 2) and Trc at 9 clocks instead of the required 3. I also tried doubling the refresh rate as a shot in the dark. I have a test point to see RAS, CAS, and WE and I will pursue that further, but it's difficult to be able to probe address or data lines.

I was hoping there might be some trick to getting it to work that our guys didn't know about 4 years ago when this board was designed. It might just turn out that this board is too noisy for these signals to work.

Thanks again for your suggestions,
Lloyd