I refer DRA75x_DRA74x_SR2.0_SR1.x_NDA_TRM_vAD.pdf,
The note of Section 26.4.4.2.1.2 Software Reset said below
NOTE: To ensure a proper operation, user software must configure settings of the OCP2SCP_TIMING register before a software reset is initiated on OCP2SCP3.
But Table 26-91 PCIe PHY Subsystem Low-Level Programming Sequence is as below.
6. Software reset the OCP2SCP3 and poll until soft reset completion is indicated in status.
See Section 26.4.4.2.1.2, Software Reset.
7. Set up division ratio between the OCP clock (PRCM.L3INIT_L4_GICLK) and SCP clock to supply the serial configuration register domains of the PCIe_PHY modules
See Section 26.4.4.2.3, OCP2SCP3 Timing Registers.
8. Set up necessary SYNC1 and SYNC2 timings to ensure no blocking of transactions over the SCP bus.
See also Section 26.4.4.2.3, OCP2SCP3 Timing Registers. After this step, the user is ready to access the PCIe PHY registers.
The OCP2SCP3 Timing Registers configure at Step 7 and 8. It is after doing Setftware Reset for OCP2SCP3.
It seems against the NOTE in Section 26.4.4.2.1.2.
Which is the correct ?
I something misunderstand ?
Best Regards
Yasuhiro Mitsui
