Boot the OMAP-L138

Well Zhang,

I might be able to shed a little light on the procedure, but I have some questions myself!

Below is copied from the sprugm7c, section 12.2:

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12.2 DSP Wake Up
Following deassertion of device reset, the DSP intializes the ARM296 so that it can execute the ARM
ROM bootloader. Upon successful wake up, the ARM places the DSP in a reset and clock gated
(SwRstDisable) state that is controlled by the LPSC and the SYSCFG modules.
Perform the following steps to wake up the DSP:
1. Write a 83E7 0B13h to the KICK0R register in the SYSCFG module.
2. Write a 95A4 F1E0h to the KICK1R register in the SYSCFG module.
3. Write the truncated DSP boot address vector to the DSP_ISTP_RST_VAL field in the host 1
configuration register (HOST1CFG) of the SYSCFG module. The least-significant bits of the boot
address are fixed at 0.
4. Write a 3h to the NEXT bit in the DSP local power sleep controller (LPSC) module control register
(PSC0.MDCTL15) to prepare the DSP module for an enable transition (to enable the clocks and all
transitioning from the SwRstDisable state to Enable state).
5. Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain
transition command register (PSC0.PTCMD) to start the state transition sequence for the DSP module.
6. Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) for
power transition sequence completion. The domain is only safely in the new state after the GOSTAT[1]
bit is cleared to 0.
7. Wait for the STATE bit field in the DSP LPSC module status register (PSC0.MDSTAT15) to change to
3h. The module is only safely in the new state after the STATE bit field changes to reflect the new
state.
8. Write a 1 to the LRST bit in PSC0.MDCTL15 to release the DSP local reset controlled by the PSC
module.

Note:
Step 8 can also be combined with Step 4. You can write a 103h to the PSC0.MDCTL15 in
Step 4 to release the DSP local reset and transition it from a SwRstDisable to Enable state.
The steps to release the DSP reset by the SYSCFG module (Steps 1-3) are only required at
device reset/system reset/warm reset. Disabling/enabling clocks to the DSP module at any
other time can be independently controlled by the PSC module alone. Guidelines to
enable/disable clocks for power management are provided in Chapter 9.

**************************************************************************************************

We've tried this procedure and it releases the DSP from reset, but have some questions about Arm access to the DSP internal memory at address 0x1180 0000.  What we want to do is load the DSP executable image via the Arm at boot time, then start the DSP executing.  So far, we haven't been able to find documentation or a application note that describes how to do this.  Step 3 above shows setting the DSP execution address, and the rest of the procedure releases the DSP from reset, but we haven't been successful so far in getting read/write access to the DSP memory while the DSP is still in reset.

Any clues?

Hi Zhang

In general from a TI software offering standpoint, it would be the DSPLINKs responsibility to re-enable the DSP and release it from the local reset.
You might find the following forum post helpful to understand the steps/sequence (specifically my post dated March 16 2010, Tuesday, 3.37pm)

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/36481/133800.aspx#133800

Regards

Mukul

Hi Gerry

Gerry Simmons said:

We've tried this procedure and it releases the DSP from reset, but have some questions about Arm access to the DSP internal memory at address 0x1180 0000.  What we want to do is load the DSP executable image via the Arm at boot time, then start the DSP executing.  So far, we haven't been able to find documentation or a application note that describes how to do this.

DSPLINK would be one way to do this (preferred way). If you were planning to implement your own scheme following the pasted guidelines, you should be able to access/load to the ARM memory after Step 7, i.e. once you have enabled the clock to the DSP SS (including L2 memories etc). By this time you should have programmed the ISTP value, and after that if you release the local reset (Step 8), DSP will start executing from the location specified in the HOST1CFG register.

Let us know if you don't see this working.

Please note that the latest version of the system guide is sprugm7d, although I don't think anything has been updated in the sections you are interested in, but I would still recommend utilizing the latest version of the system guide. .

Regards

Mukul