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am335x u-boot fails

Other Parts Discussed in Thread: AM3352

Hi!
We designed custom single-board controller around am3352 SoC. We uses NAND chip by Micron as general storage.
At first generation of design there was a MT29F4G08ABADA (4Gb ~ 512MB), and everything was fine.
We used u-boot build "freezed" at tag 2013.07 with some changes concerns our board, and
left it "as is" for a years.
But now we need modification with more disk space, and we decided to use MT29F16G08ABABA chip (16Gb ~ 2GB).
Suddenly ( :-) ) new board began to fail with this chip! Some investigations... and I (I am programmer in our workgroup) see,
that old u-boot failed at NAND detection. And there was huge code for the 3 years, including ONFI NAND support. And also
linux like Kbuild configuration, driver model an so on.

Something else... We use 2 builds of u-boot:
1. "Fabrication" (in other words "debrick") build, that boots over dhcp/tftp, and automaticly writes NAND partitions from MLO to kernel.
2. "Main"-standalone build, that boots from NAND.

Ok, I got fresh u-boot clone from denx.de , dragged our custom code to new source-tree, and now we have:
- "Fabrication" build - seems works fine, and I can see how it processes at console, there are no errors, except messages like this:

CACHE: Misaligned operation at range [81000000, 81059672]

- NAND chip detection - OK;
- u-boot "nand info" command, it seems, shows correct:
=> nand info

Device 0: nand0, sector size 512 KiB
  Page size       4096 b
  OOB size         224 b
  Erase size    524288 b
  subpagesize     1024 b
  options     0x4000000c
  bbt options 0x       0
- "nand write" operation reports "OK";
- nand read partition ok, and md shows correct hexdump (at few start segments that we can check by eyes)
But after debrick.scr script execution, which ends with "go 20000;" (ROM code address, isnt?)
We have:
## Starting application at 0x00020000 ...
prefetch abort
pc : [<00020004>]          lr : [<8ff700b5>]
reloc pc : [<f08b1004>]    lr : [<808010b5>]
sp : 8ef44cf8  ip : 8ef44ad4     fp : 8ffb69e0
r10: 00000002  r9 : 8ef4eed8     r8 : 00000000
r7 : 8ef96330  r6 : 00020000     r5 : 00000002  r4 : 8ef96334
r3 : 00020000  r2 : 8ef96334     r1 : 8ef96334  r0 : 00000001
Flags: nzCv  IRQs off  FIQs on  Mode SVC_32
Resetting CPU ...

Any suggestions?
Thanks for help, ideas... right questions.

  • Hi,

    I will ask the software team to comment. They will respond directly here.
  • Problem solved!

    Answer to my question by myself:

    There no any bug at code, wrong instruction or initialisation or something similar. Interrupt generates by CPU core itself. Cortex-A8 contains unit, called System Control Coprocessor, it can control memory operations such as read, write and fetching instruction. And it can be configured so that some adress ranges are protected for particular operations. And if some code try to access to protected regions SCC straight generates interrupt with either "data abort" or "prefetch abort" vector.

    Configuring of SCC is closely related with ICACHE and DCACHE. Huh... It seems... It's very deep magic for me. I have no so bare-metal coding experience... So, I just switched off ICACHE and DCACHE in my "restore_flash" u-boot build by this macro:

    #define CONFIG_SYS_DCACHE_OFF
    #define CONFIG_SYS_ICACHE_OFF

    Hooray! Everything is OK!

    "go 20000" command brings to ROM code!

    P.S. I really tried to dig, where u-boot configurate this address range protection. I learned some new terms like  TLB, CP15, CPSR and so. But I can't locate, where and how new u-boot lock address 0x20000 to fetching instructions.
    It seems, it is not at board.c (in all levels) , not in start.S, not in virt-v7.c but something in arch/arm/cpu/armv7. So It can-not be reimplemented in board/<vendor>/<custom code> branch.