CCS REMARK: L1D bug may be triggered by this execute packet

Bryan,

What device is this for? 

Is this a message from the assembler?

This sounds like it's a warning regarding a Si bug that we have on some of the C64x+ devices, which we used the compiler to work around.  Below is a cut an paste from one of the errata's and the code mentioned would fall into that.  The existing compiler will not generate this code, and the assembler will toss out an warning, because it only knows that it's C64x+ and not say C6455 device which has the issue.  I'd either verify the addresses are not in the same cache line, or modify the code so it doesn't have a double predication.

Details:

Under certain conditions, parallel loads with predication to the same cache line may
cause victims to be dropped and/or the DMA to hang.
All of the following conditions must be true in order for this problem to occur:
1. Two LD instructions in parallel.
2. Both are LDs to the same cache line (upper 26 address bits are the same).
3. The LD using T1 is predicated and the predicate is false.
4. The LD using T2 is either not predicated, or is predicated and the predicate is true.
5. The cache line is absent from the cache.
6. The two other lines in the same L1D set are valid.
7. The LRU cache line in the set is dirty.

Results:
· L1D informs L2 to expect a victim for the affected set.
· L2 stalls DMAs with addresses that correspond to that set.
Note: DMA includes accesses from IDMA, EDMA, and any external masters,
such as PCI or other CPUs.
· L1D processes the true-predicated request correctly.
· L1D does not send the indicated victim.
Impact: If the load instruction reads a cacheable location:
· The updated data in the LRU line gets dropped.
· DMA accesses whose addresses match the affected set hang.
If the load instruction reads a non-cacheable location:
· L1D retains the updated data from the LRU line.
· DMA reads may see stale data if the LRU line's address is in L2 memory.

Workaround(s): Use Code Gen patch 6.0.3 (available on update advisor) to recompile your source code
and avoid this issue. Libraries supplied by TI will be re-released using the 6.0.3 compiler
patch. Customer-generated libraries from TI's third-party supplier may also need to be
recompiled.
For existing object code and libraries, an available Perl script can determine locations of
parallel predicated loads that may fail. The script is available at the same update advisor
location as the Code Gen patch.

Best Regards,

Chad