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EDMA3 problem on OMAP L138

ewan browne
Prodigy 50 points
Other Parts Discussed in Thread: OMAPL138

I am trying to use EDMA3 on the L138 without the edma driver or the CSL. In the first instance I want to tie the EDMA to the  timer3 :12 event on EDMA1_CC0 using TC2  and event channel 26. I have verified that the event is occuring and can even see my linked  parameter RAM tables being updated when I change (for debug purposes) parameters in my linked PaRAM set and the event PaRAM set gets updated. Unfortunately I have never seen any data being written to the destination. Is there some other setting  (ie slave memory setting ) that needs to be made external to the DMA module.

Heres what my code looks like

 

 void DAC_DMA_Init(Uint32 EventID, L138_Edma3ccParamSetRegs_t *DMA_parmSet)

{

 

USTIMER_reset(); // make sure timer 3 is off

 

 

OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMACC1, PSC_ENABLE);

 

 

 

OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMACC1, PSC_ENABLE);

 

 

OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMACC1, PSC_ENABLE);

 

OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMATC2, PSC_ENABLE);

 

EDMA1_CC0->PARAMSET[EventID] = *DMA_parmSet;  // Implement the T3:12 synchronization Event

 

EDMA1_CC0->PARAMSET[127] = *DMA_parmSet;  // Populate the T3:12 Link parameter set at 127

 

 

EDMA1_CC0->ECR = 0xFFFFFFFF ;  // Clear any pending Event

EDMA1_CC0->EESR = 1 << EventID; // Enable Timer Event E26

 }

 

 

 

void test_DMA(void)

 

{

int index;

L138_Edma3ccParamSetRegs_t *DAC_paramSet;

 

 

 

DAC_paramSet->OPT = 0x00000100; // FWID = 16 bit

DAC_paramSet->SRC = (Uint32)&r[2048]; // Source Address - sine table from IFFT

DAC_paramSet->DST = (Uint32)&(FPGA_DAC->DAC_Data); // Dest Address

DAC_paramSet->A_B_CNT = 0x04000002 ; //1024 bytes, 2 bytes = 1 16 bit word

DAC_paramSet->SRC_DST_BIDX = 0x00000002; // Source idx increments 2 (Int16) locations

DAC_paramSet->LINK_BCNTRLD = 0x04004FE0; // Value to reload after transfer, PaRAM set 127

DAC_paramSet->CCNT = 0;

DAC_DMA_Init( L138_EDMA3_CHA_TIMER64P3_EVT12, DAC_paramSet);

init_DACTIMER(1000);  // start timer 3 and data output

 

 

  • 0
    TI__Mastermind 29111 points

    I see you loading the PaRAM[127], but are you loading PaRAM[26]?

    E Browne said:
    EDMA1_CC0->PARAMSET[127] = *DMA_parmSet;  // Populate the T3:12 Link parameter set at 127

    PaRAM[26] is what the EDMA CC actually uses when it receives an event from the Timer.  After PaRAM[26] is exhausted, the EDMA CC will reload it with the contents of PaRAM[127] as you have specified using this line of code:

    E Browne said:
    DAC_paramSet->LINK_BCNTRLD = 0x04004FE0; // Value to reload after transfer, PaRAM set 127

  • 0 in reply to Gus Martinez
    Prodigy 50 points

    The Event_ID was passed in as a parameter - L138_EDMA3_CHA_TIMER64P3_EVT12  equates to 26 per the TI CSL.

    However I have solved the problem I needed to set CCNT to 1 and this cannot be 0 as per item 4 in appendix A2 of the DMA manual. I had overlooked this believing that an A dimension sync didnt need any C dimension parmaetrs set. Also for anyone else trying this make sure you have all your SCR bridges turned on in the PSC

  • 0 in reply to ewan browne
    TI__Guru* 83935 points

    OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMACC1, PSC_ENABLE);

    OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMACC1, PSC_ENABLE);

     

    OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMACC1, PSC_ENABLE);

     

    OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMATC2, PSC_ENABLE);

     

    This looked wrong too, I didn't see TC0 and TC1 enable, and CC0/TC0/TC1 are in PSC0 where as CC1/TC2 are in PSC1.

    Good to hear that the problem is resolved.

  • 0 in reply to Mukul Bhatnagar
    Prodigy 50 points

    Thats rIght - CC1 has only one TC attached to it and therefore you only need to turn on for this DMA channel

     

     

    OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMACC1, PSC_ENABLE);

     

    // OMAPL138_lpscTransition(PSC0, DOMAIN0, LPSC_EDMATC0, PSC_ENABLE);

     

    // OMAPL138_lpscTransition(PSC0, DOMAIN0, LPSC_EDMATC1, PSC_ENABLE);

    OMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EDMATC2, PSC_ENABLE);

    Where TC2 is called out as TC0 in most of the documentation but is TC2 in CCS4 (i.e. viewing registers)

  • 0 in reply to ewan browne
    TI__Guru* 83935 points

    E Browne said:
    Where TC2 is called out as TC0 in most of the documentation but is TC2 in CCS4 (i.e. viewing registers)

    Yes, I see a lot of places where we are still calling it TC2 , from a datasheet/software convention we would like to see these as 2 instances of the EDMA3 module (CC+TC) , EDMA_0 and EDMA_1 , with each having a CC0 and variable # of TCs , (EDMA3_0_CC0 , EDMA3_0_TC0, EDMA3_0_TC1 and EDMA3_1_CC0 and EDMA3_1_TC0).

    It is likely that using EDMA3_0/1 will make the registers names very long for CCS register view. Thanks for pointing out irrespective, will see if this can be aligned better.

    Regards

    Mukul