Other Parts Discussed in Thread: TUSB1210
Hi ,
We have our custom board + TUSB1210 on USB port 3 with ULPI turn on.
But the USB port3 phy keep status busy bit on when usb driver try to configure usb port3 phy and then timeout.
[ 3.071451] dwc3_ulpi_init:83=========
[ 3.075228] ulpi_register_interface:218========
[ 3.079776] ulpi_register:163======
[ 3.083291] ulpi_write:30======
[ 3.086444] dwc3_ulpi_write:70===== 0xc280 , reg=0x25600aa
[ 3.091953] dwc3_writel:70 === addr fa91c280 value 025600aa
[ 3.097561] dwc3_readl:46 === addr fa91c280 value 02d600aa
.
.
.
[ 8.607307] dwc3_readl:46 === addr fa91c280 value 02d600aa
[ 8.612813] dwc3_ulpi_busyloop:39==== timeout
[ 8.617290] dwc3 48910000.usb: failed to register ULPI interface
[ 8.623358] dwc3: probe of 48910000.usb failed with error -110
Do you know what cause will lead to this situation ?
Attach my boot log and dts for your reference, t hanks.
Best,
Andy
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
/ {
model = "TI DRA742 20160921";
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2048 MB */
// reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
reserved_mem: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ipu2_cma_pool: ipu2_cma@95800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x95800000 0x0 0x3800000>;
reusable;
status = "okay";
};
dsp1_cma_pool: dsp1_cma@99000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x99000000 0x0 0x4000000>;
reusable;
status = "okay";
};
ipu1_cma_pool: ipu1_cma@9d000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9d000000 0x0 0x2000000>;
reusable;
status = "okay";
};
dsp2_cma_pool: dsp2_cma@9f000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9f000000 0x0 0x800000>;
reusable;
status = "okay";
};
};
#if 0
aliases {
display0 = &hdmi0;
display1 = &fpd_disp;
//sound0 = &snd0;
sound1 = &hdmi;
//i2c7 = &disp_ser;
};
#endif
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
evm_3v3_sw: fixedregulator-evm_3v3_sw {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sw";
vin-supply = <&sysen1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&evm_3v3_sw>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vmmcwl_fixed: fixedregulator-mmcwl {
compatible = "regulator-fixed";
regulator-name = "vmmcwl_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
//gpio = <&gpio5 8 0>; /* gpio5_8 */
startup-delay-us = <70000>;
regulator-always-on;
regulator-boot-on;
};
#if 0
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
};
#endif
vtt_fixed: fixedregulator-vtt {
compatible = "regulator-fixed";
regulator-name = "vtt_fixed";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
vin-supply = <&sysen2>;
//gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
#if 0
snd0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC3L", "Mic Jack",
"MIC3R", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
system-clock-frequency = <11289600>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&atl_clkin2_ck>;
};
};
#endif
hdmi0: connector@1 {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder@1 {
compatible = "ti,dra7evm-tpd12s015";
pinctrl-names = "i2c", "ddc";
pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
ddc-i2c-bus = <&i2c2>;
mcasp-gpio = <&mcasp8>;
gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
<&pcf_hdmi 5 0>, /* P5, LS OE */
<&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint@0 {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint@0 {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&dra7_pmx_core {
usb3_pins: pinmux_usb3_pins {
pinctrl-single,pins = <
0x3a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_dat7.usb3_ulpi_clk GPIO1_25 AB5
0x39c (PIN_OUTPUT | MUX_MODE3) // mmc3_dat6.usb3_ulpi_stp GPIO1_24 AB8
0x398 (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_dat5.usb3_ulpi_dir GPIO1_23 AD6
0x394 (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_dat4.usb3_ulpi_nxt GPIO1_22 AC8
0x390 (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_dat3.usb3_ulpi_d0 GPIO7_2 AC3
0x38c (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_dat2.usb3_ulpi_d1 GPIO7_1 AC9
0x388 (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_dat1.usb3_ulpi_d2 GPIO7_0 AC6
0x384 (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_dat0.usb3_ulpi_d3 GPIO6_31 AC7
0x380 (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_cmd.usb3_ulpi_d4 GPIO6_30 AC4
0x37c (PIN_INPUT_PULLDOWN | MUX_MODE3) // mmc3_clk.usb3_ulpi_d5 GPIO6_29 AD4
0x378 (PIN_INPUT_PULLDOWN | MUX_MODE3) // gpio6_11.usb3_ulpi_d6 GPIO6_11 AB4
0x374 (PIN_INPUT_PULLDOWN | MUX_MODE3) // gpio6_10.usb3_ulpi_d7 GPIO6_10 AC5
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
pinctrl-single,pins = <
/* this pin is used as a GPIO via mcasp */
0x2fc (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
>;
};
hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
pinctrl-single,pins = <
0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
>;
};
hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
pinctrl-single,pins = <
0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
>;
};
mmc1_pins_default: pinmux_mmc1_default_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_hs: pinmux_mmc1_hs_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins {
pinctrl-single,pins = <
0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_hs: mmc2_pins_hs {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_ddr_1_8v: pinmux_mmc2_ddr_1_8v_pins {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc2_pins_hs200_1_8v: mmc2_pins_hs200_1_8v {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
mmc4_pins_default: mmc4_pins_default {
pinctrl-single,pins = <
0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
0x3ec (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
0x3fC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
mmc4_pins_hs: mmc4_pins_hs {
pinctrl-single,pins = <
0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
0x3ec (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
0x3fC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
mmc4_pins_sdr12: mmc4_pins_sdr12 {
pinctrl-single,pins = <
0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
0x3eC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
0x3fc (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
mmc4_pins_sdr25: mmc4_pins_sdr25 {
pinctrl-single,pins = <
0x3e8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
0x3eC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
0x3f0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
0x3f4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
0x3f8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
0x3fc (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
>;
};
};
&dra7_iodelay_core {
uart3_pins_default: pinmux_uart3_pins {
pinctrl-single,pins = <
0x34c (PIN_INPUT | MUX_MODE4) /* mcasp5_axr0.uart3_rxd */
0x350 (PIN_OUTPUT | MUX_MODE4) /* mcasp5_axr1.uart3_txd */
>;
};
mmc1_iodelay_ddr50_rev11_conf: mmc1_iodelay_ddr50_rev11_conf {
pinctrl-single,pins = <
0x618 (A_DELAY(572) | G_DELAY(540)) /* CFG_MMC1_CLK_IN */
0x624 (A_DELAY(0) | G_DELAY(600)) /* CFG_MMC1_CMD_IN */
0x630 (A_DELAY(403) | G_DELAY(120)) /* CFG_MMC1_DAT0_IN */
0x63c (A_DELAY(23) | G_DELAY(60)) /* CFG_MMC1_DAT1_IN */
0x648 (A_DELAY(25) | G_DELAY(60)) /* CFG_MMC1_DAT2_IN */
0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
0x620 (A_DELAY(1525) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x62c (A_DELAY(55) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
>;
};
mmc1_iodelay_ddr50_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
pinctrl-single,pins = <
0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */
0x620 (A_DELAY(1271) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
0x624 (A_DELAY(229) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */
0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x630 (A_DELAY(850) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */
0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x638 (A_DELAY(20) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x63C (A_DELAY(468) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */
0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x648 (A_DELAY(466) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */
0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x654 (A_DELAY(399) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
0x65C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
>;
};
mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
pinctrl-single,pins = <
0x620 (A_DELAY(1063) | G_DELAY(17)) /* CFG_MMC1_CLK_OUT */
0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x62c (A_DELAY(23) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x644 (A_DELAY(2) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
>;
};
mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
pinctrl-single,pins = <
0x620 (A_DELAY(600) | G_DELAY(400)) /* CFG_MMC1_CLK_OUT */
0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
0x638 (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
>;
};
mmc2_iodelay_hs200_1_8v_rev11_conf: mmc2_iodelay_hs200_1_8v_rev11_conf {
pinctrl-single,pins = <
0x190 (A_DELAY(621) | G_DELAY(600)) /* CFG_GPMC_A19_OEN */
0x194 (A_DELAY(300) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
0x1a8 (A_DELAY(739) | G_DELAY(600)) /* CFG_GPMC_A20_OEN */
0x1ac (A_DELAY(240) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1b4 (A_DELAY(812) | G_DELAY(600)) /* CFG_GPMC_A21_OEN */
0x1b8 (A_DELAY(240) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1c0 (A_DELAY(954) | G_DELAY(600)) /* CFG_GPMC_A22_OEN */
0x1c4 (A_DELAY(60) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1d0 (A_DELAY(1340)| G_DELAY(420)) /* CFG_GPMC_A23_OUT */
0x1d8 (A_DELAY(935) | G_DELAY(600)) /* CFG_GPMC_A24_OEN */
0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1e4 (A_DELAY(525) | G_DELAY(600)) /* CFG_GPMC_A25_OEN */
0x1e8 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1f0 (A_DELAY(767) | G_DELAY(600)) /* CFG_GPMC_A26_OEN */
0x1f4 (A_DELAY(225) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x1fc (A_DELAY(565) | G_DELAY(600)) /* CFG_GPMC_A27_OEN */
0x200 (A_DELAY(60) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x364 (A_DELAY(969) | G_DELAY(600)) /* CFG_GPMC_CS1_OEN */
0x368 (A_DELAY(180) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
>;
};
mmc2_iodelay_hs200_1_8v_rev20_conf: mmc2_iodelay_hs200_1_8v_rev20_conf {
pinctrl-single,pins = <
0x190 (A_DELAY(274) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
0x194 (A_DELAY(162) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
0x1a8 (A_DELAY(401) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
0x1ac (A_DELAY(73) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1b4 (A_DELAY(465) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
0x1b8 (A_DELAY(115) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1c0 (A_DELAY(633) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
0x1c4 (A_DELAY(47) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1d0 (A_DELAY(935) | G_DELAY(280)) /* CFG_GPMC_A23_OUT */
0x1d8 (A_DELAY(621) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1e4 (A_DELAY(183) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1f0 (A_DELAY(467) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x1fc (A_DELAY(262) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
0x200 (A_DELAY(46) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x364 (A_DELAY(684) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
0x368 (A_DELAY(76) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
>;
};
mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
pinctrl-single,pins = <
0x18c (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */
0x1a4 (A_DELAY(274) | G_DELAY(240)) /* CFG_GPMC_A20_IN */
0x1b0 (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A21_IN */
0x1bc (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A22_IN */
0x1c8 (A_DELAY(514) | G_DELAY(360)) /* CFG_GPMC_A23_IN */
0x1d4 (A_DELAY(187) | G_DELAY(120)) /* CFG_GPMC_A24_IN */
0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
0x1ec (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A26_IN */
0x1f8 (A_DELAY(121) | G_DELAY(60)) /* CFG_GPMC_A27_IN */
0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
0x194 (A_DELAY(174) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
0x1ac (A_DELAY(168) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1b4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
0x1b8 (A_DELAY(136) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
0x1c4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1d0 (A_DELAY(879) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
0x1e8 (A_DELAY(34) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1f0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
0x1f4 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x1fc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
0x368 (A_DELAY(11) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
>;
};
mmc2_iodelay_ddr_1_8v_rev20_conf: mmc2_iodelay_ddr_1_8v_rev20_conf {
pinctrl-single,pins = <
0x18c (A_DELAY(270) | G_DELAY(0)) /* CFG_GPMC_A19_IN */
0x1a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_IN */
0x1b0 (A_DELAY(170) | G_DELAY(0)) /* CFG_GPMC_A21_IN */
0x1bc (A_DELAY(758) | G_DELAY(0)) /* CFG_GPMC_A22_IN */
0x1c8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */
0x1d4 (A_DELAY(81) | G_DELAY(0)) /* CFG_GPMC_A24_IN */
0x1e0 (A_DELAY(286) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
0x1ec (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_IN */
0x1f8 (A_DELAY(123) | G_DELAY(0)) /* CFG_GPMC_A27_IN */
0x360 (A_DELAY(346) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
0x194 (A_DELAY(55) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
0x1ac (A_DELAY(422) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
0x1b4 (A_DELAY(642) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
0x1b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
0x1c4 (A_DELAY(128) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
0x1d0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
0x1dc (A_DELAY(395) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
0x1f0 (A_DELAY(623) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
0x1fc (A_DELAY(54) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
>;
};
mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
pinctrl-single,pins = <
0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
0x848 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
0x84c (A_DELAY(96) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
0x870 (A_DELAY(582) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
0x87c (A_DELAY(391) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
0x888 (A_DELAY(561) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
0x894 (A_DELAY(588) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
>;
};
mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
pinctrl-single,pins = <
0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
0x848 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
0x84c (A_DELAY(307) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
0x870 (A_DELAY(785) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
0x87c (A_DELAY(613) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
0x888 (A_DELAY(683) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
0x894 (A_DELAY(835) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
>;
};
mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
pinctrl-single,pins = <
0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
0x848 (A_DELAY(2651) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
0x84c (A_DELAY(1572) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
0x870 (A_DELAY(1913) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
0x87c (A_DELAY(1721) | G_DELAY(0)) /* CFG_UART2_RTSN_IN */
0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
0x888 (A_DELAY(1891) | G_DELAY(0)) /* CFG_UART2_RXD_IN */
0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
0x894 (A_DELAY(1919) | G_DELAY(0)) /* CFG_UART2_TXD_IN */
0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
>;
};
mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
pinctrl-single,pins = <
0x840 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_CTSN_IN */
0x848 (A_DELAY(1147) | G_DELAY(0)) /* CFG_UART1_CTSN_OUT */
0x84c (A_DELAY(1834) | G_DELAY(0)) /* CFG_UART1_RTSN_IN */
0x850 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OEN */
0x854 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART1_RTSN_OUT */
0x870 (A_DELAY(2165) | G_DELAY(0)) /* CFG_UART2_CTSN_IN */
0x874 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OEN */
0x878 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_CTSN_OUT */
0x87c (A_DELAY(1929) | G_DELAY(64)) /* CFG_UART2_RTSN_IN */
0x880 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OEN */
0x884 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RTSN_OUT */
0x888 (A_DELAY(1935) | G_DELAY(128)) /* CFG_UART2_RXD_IN */
0x88c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OEN */
0x890 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_RXD_OUT */
0x894 (A_DELAY(2172) | G_DELAY(44)) /* CFG_UART2_TXD_IN */
0x898 (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OEN */
0x89c (A_DELAY(0) | G_DELAY(0)) /* CFG_UART2_TXD_OUT */
>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tps659038: tps659038@58 {
compatible = "ti,tps659038";
reg = <0x58>;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
regulators {
smps123_reg: smps123 {
/* VDD_MPU */
regulator-name = "smps123";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps45_reg: smps45 {
/* VDD_DSPEVE */
regulator-name = "smps45";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps6_reg: smps6 {
/* VDD_GPU - over VDD_SMPS6 */
regulator-name = "smps6";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps7_reg: smps7 {
/* CORE_VDD */
regulator-name = "smps7";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
smps8_reg: smps8 {
/* VDD_IVAHD */
regulator-name = "smps8";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps9_reg: smps9 {
/* VDDS1V8 */
regulator-name = "smps9";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> SDIO */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo2_reg: ldo2 {
/* VDD_RTCIO */
/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
regulator-name = "ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo9_reg: ldo9 {
/* VDD_RTC */
regulator-name = "ldo9";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-bypass;
};
ldoln_reg: ldoln {
/* VDDA_1V8_PLL */
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldousb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
/* REGEN1 is unused */
regen2: regen2 {
/* Needed for PMIC internal resources */
regulator-name = "regen2";
regulator-boot-on;
regulator-always-on;
};
/* REGEN3 is unused */
sysen1: sysen1 {
/* PMIC_REGEN_3V3 */
regulator-name = "sysen1";
regulator-boot-on;
regulator-always-on;
};
sysen2: sysen2 {
/* PMIC_REGEN_DDR */
regulator-name = "sysen2";
regulator-boot-on;
regulator-always-on;
};
};
};
};
pcf_lcd: gpio@20 {
status = "disabled";
compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcf_gpio_21: gpio@21 {
status = "disabled";
compatible = "ti,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
#if 0
tlv320aic3106: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
status = "disabled";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
//status = "okay";
status = "disabled";
/* Regulators */
AVDD-supply = <&evm_3v3_sw>;
IOVDD-supply = <&evm_3v3_sw>;
DRVDD-supply = <&evm_3v3_sw>;
DVDD-supply = <&aic_dvdd>;
};
#endif
};
i2c_p3_exp: &i2c2 {
status = "okay";
clock-frequency = <400000>;
tvp_5158: tvp5158@58 {
compatible= "ti,tvp5158";
reg = <0x58>;
port {
tvp_decoder: endpoint@0 {
remote-endpoint = <&vin2a>;
//channels = <0 2 4 6>;
channels = <0>;
//pixel-mux;
//pclk-sample = <0>;
};
};
};
pcf_hdmi: gpio@26 {
compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
p1 {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "vin6_sel_s0";
};
};
ov10633@37 {
status = "disabled";
compatible = "ovti,ov10633";
reg = <0x37>;
mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
port {
onboardLI: endpoint {
//remote-endpoint = <&vin1a>;
remote-endpoint = <&vin4b>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
};
};
};
disp_ser: serializer@1b {
status = "disabled" ;
compatible = "ti,ds90uh925q";
reg = <0x1b>;
#address-cells = <1>;
#size-cells = <0>;
ranges = <0x2c 0x2c>,
<0x1c 0x1c>;
disp_des: deserializer@2c {
compatible = "ti,ds90uh928q";
reg = <0x2c>;
slave-mode;
};
/* TLC chip for LCD panel power and backlight */
fpd_disp: tlc59108@1c {
status = "disabled";
reg = <0x1c>;
compatible = "ti,tlc59108-fpddisp";
enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
/* P0, SEL_GPMC_AD_VID_S0 */
port@lcd3 {
fpd_in: endpoint {
remote-endpoint = <&dpi_out3>;
};
};
};
};
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
};
&mcspi1 {
status = "okay";
};
&mcspi2 {
status = "okay";
};
&uart1 {
status = "disabled";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
/* gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; */
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
};
&mmc1 {
status = "okay";
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
//cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <192000000>;
pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_hs>;
pinctrl-2 = <&mmc1_pins_sdr12>;
pinctrl-3 = <&mmc1_pins_sdr25>;
pinctrl-4 = <&mmc1_pins_sdr50>;
pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_rev11_conf>;
pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_rev20_conf>;
pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
max-frequency = <192000000>;
pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev11_conf>;
pinctrl-3 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev20_conf>;
pinctrl-4 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev11_conf>;
pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>;
};
&mmc4 {
status = "okay";
vmmc-supply = <&vmmcwl_fixed>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
ti,non-removable;
pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
};
};
&oppdm_mpu {
vdd-supply = <&smps123_reg>;
};
&oppdm_dspeve {
vdd-supply = <&smps45_reg>;
};
&oppdm_gpu {
vdd-supply = <&smps6_reg>;
};
&oppdm_ivahd {
vdd-supply = <&smps8_reg>;
};
&oppdm_core {
vdd-supply = <&smps7_reg>;
};
&qspi {
//status = "okay";
status = "disabled";
spi-max-frequency = <64000000>;
m25p80@0 {
compatible = "s25fl256s1";
spi-max-frequency = <64000000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000040000>;
};
partition@1 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@2 {
label = "QSPI.u-boot-spl-os";
reg = <0x00140000 0x00080000>;
};
partition@3 {
label = "QSPI.u-boot-env";
reg = <0x001c0000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot-env.backup1";
reg = <0x001d0000 0x0010000>;
};
partition@5 {
label = "QSPI.kernel";
reg = <0x001e0000 0x0800000>;
};
partition@6 {
label = "QSPI.file-system";
reg = <0x009e0000 0x01620000>;
};
};
};
&omap_dwc3_1 {
//extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
//extcon = <&extcon_usb2>;
};
&usb1 {
status = "ok";
dr_mode = "host";
};
&usb2 {
status = "ok";
dr_mode = "host";
};
&usb3 {
pinctrl-names = "default";
pinctrl-0 = <&usb3_pins>;
status = "ok";
dr_mode = "host";
snps,hsphy_interface = "ulpi";
};
&elm {
status = "okay";
};
&gpmc {
status = "disabled";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
&usb2_phy2 {
phy-supply = <&ldousb_reg>;
};
&gpio7 {
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&mac {
status = "okay";
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&dcan1 {
status = "ok";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin1_ck>,
<&atl_clkin2_ck>;
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
assigned-clock-rates = <0>, <0>, <361267200>,
<11289600>, <11289600>;
status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "disabled";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&mcasp8 {
/* not used for audio. only the AXR2 pin is used as GPIO */
status = "disabled";
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};
&mmu0_dsp1 {
status = "okay";
};
&mmu1_dsp1 {
status = "okay";
};
&mmu0_dsp2 {
status = "okay";
};
&mmu1_dsp2 {
status = "okay";
};
&mmu_ipu1 {
status = "okay";
};
&mmu_ipu2 {
status = "okay";
};
&ipu2 {
status = "okay";
memory-region = <&ipu2_cma_pool>;
mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
timers = <&timer3>;
watchdog-timers = <&timer4>, <&timer9>;
};
&ipu1 {
status = "okay";
memory-region = <&ipu1_cma_pool>;
mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
timers = <&timer11>;
watchdog-timers = <&timer7>, <&timer8>;
};
&dsp1 {
status = "okay";
memory-region = <&dsp1_cma_pool>;
mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
timers = <&timer5>;
watchdog-timers = <&timer10>;
};
&dsp2 {
status = "okay";
memory-region = <&dsp2_cma_pool>;
mboxes = <&mailbox6 &mbox_dsp2_ipc3x>;
timers = <&timer6>;
};
&dss {
status = "okay";
vdda_video-supply = <&ldoln_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@lcd3 {
reg = <2>;
dpi_out3: endpoint {
remote-endpoint = <&fpd_in>;
data-lines = <24>;
};
};
};
};
&hdmi {
status = "ok";
vdda-supply = <&ldo3_reg>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
#if 0
&vip1 {
status = "okay";
};
video_in: &vin1a {
status = "okay";
endpoint@0 {
slave-mode;
remote-endpoint = <&onboardLI>;
};
};
#endif
&vip2 {
status = "okay";
};
video_in: &vin4b {
status = "okay";
endpoint@0 {
slave-mode;
remote-endpoint = <&onboardLI>;
};
};
#include "dra7xx-jamr3.dtsi"
#if 0
&tvp_5158{
mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>, /*CAM_FPD_MUX_S0*/
<&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>; /*SEL_TVP_FPD*/
};
#endif
