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Can more than 1 DSP get a GPIO sourced interrupt?

Christopher Peters
Genius 3380 points
Other Parts Discussed in Thread: AM5728, 66AK2H12

This is a question for the AM5728, but is applicable to most any multi-core DSP I would assume. 

If I have a signal coming in on a GPIO pin, can that signal be monitored as an interrupt on more than one core at a time?

For example, suppose I want to use a 1 PPS GPS signal to synchronize multiple DSP cores.

  • 0
    TI__Guru**** 393215 points

    Yes, each DSP has its own interrupt controller.

  • 0 in reply to Biser Gatchev-XID
    Genius 3380 points
    Yes, I understand that, I was thinking more along the lines of having multiple cores all calling the GPIO Init function. I guess as long as they do not conflict with each other that is ok?
  • 0 in reply to Christopher Peters
    TI__Genius 17720 points

    I think this should be possible. AM572x has flexible interrupt routing via IRQ_CROSSBAR. See 18.4.6.4 IRQ_CROSSBAR Module Functional Description in the TRM.

  • 0 in reply to Christopher Peters
    TI__Guru**** 393215 points
    What is this GPIO Init function?
  • 0 in reply to Biser Gatchev-XID
    Genius 3380 points
    Maybe this is different with Sys/Bios, which is what the DSPs are running in my case. To use the GPIO you have to initialize the GPIO_v1_Config struct, which is composed of the GPIO_PinConfig and GPIO_CallbackFxn structs and then call GPIO_Init();. To date, using two DSPs, each DSP has dedicated GPIO pins, so the content of these structs is mutually exclusive. Following that I setup the desired crossbars. To date these have always been one GPIO IRQ to one DSP IRQ and another GPIO IRQ to another DSP IRQ.

    What I have not yet done, but see the need for, is to have the same GPIO port/pin resource in two different DSP's, both calling GPIO_Init and then having one GPIO IRQ connected to different DSP IRQ's.
  • 0 in reply to Stanislav Stilyanov
    Genius 3380 points
    I'll take a look at the TRM for Crossbar again. Thanks.
  • 0 in reply to Christopher Peters
    TI__Genius 12805 points
    Just to add to what Christopher Peters said:

    Your generic question is the following - can the system send the same interrupt to multiple hosts (or CPUs or Cores)
    The answer is YES

    For the Sitara family it is exactly what Christoper said - each Crossbar is independent, all crossbars have the same input events, and each crossbar is connected to a different host (CPU or DMA) so it is possible to connect an event to multiple host. The question is who clears the event and how to deal with race conditions when more than one interrupt occurs.

    For the DSP family (K2H, K2K, C667X) the answer is the same but the implementation is a little bit different. These devices have Central Interrupt Controllers or CIC. Each CIC is connected to other hosts. For example, in 66AK2H12 CIC0 is connected to the first 4 DSP cores, CIC1 is connected to DSP cores 4,5,6,and 7 and CIC 2 is connected to the EDMA, Hyperlink and the A15. IN addition the A15 has its own GIC - General Interrupt controller. Looking at CIC 0 (device user's guide) you can see that some output signals are connected to a specific core, and some are defined as broadcast signals, means that the same output is connected to multiple cores.

    Again, you need to think what to do AFTER interrupt occurs- who clears it, and so on.

    Ran