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What is the lowest latency ADC/DAC/DSP solution? (goal is <1ns total latency for ADC+DAC+DSP)

Other Parts Discussed in Thread: 66AK2L06, ADC32RF80, RFSDK

What is the lowest latency ADC/DAC/DSP solution?

our design goal is  less than 1 ns total latency for ADC+DAC+DSP, but would like to hear opinions even as low as 10 ns latency.  

we guess that the 66AK2L06 Evaluation Module is a good start, but are less sure what ADC and DAC evaluation modules may be compatible and may have under 1ns latency (including any pipeline delays).  we may need to go much higher than 1 GHz sampling, if there are pipelines in the ADC or DAC.

our preference is to build a prototype using evaluation boards

Some ballpark goals/needs for the system are:

1) >1Gsample/s,  >9 bits, ADC  with conversion latency <250 ps including any pipeline delays, etc
2) >1Gsample/s,  >9 bits, DAC  with conversion latency <250 ps including any pipeline delays, etc
3) DSP core capable of implementing a 6th order FIR/IIR filter with latency <250 ps per update
4) full-instantaneous-bandwidth ADC and DAC (no sampling/decimation)

ideally, the net latency through the DSP core, ADC, and DAC would be <500 ps,
and preference is usually ARM cores, if that is an option.

if you cannot suggest a <1 ns latency solution,
what is the highest rate ADC+DAC+DSP you might recommend?

thanks 

t

  • Hi Thomas,

    I've forwarded this to the ADC experts. Their feedback will be posted directly here.

    Best Regards,
    Yordan
  • Hello

    The latency is lower than we have used for JESD204B subsystems with 66AK2L06.  

      a) there is a combination of ADC - if it has a decimating digital filter, the ADC latency is more than your budget.

      b) the 66AK2L06 has 4 JESD204B lanes, the DFE that follows this highest sample rate is 368.64Msps complex.  This is higher than your budget.

      c) the highest rate with signal processing bypass that DFE supports is 122.88Msps in PG1, and 184.32Msps in PG2.

      d) after the DFE there are buffers in IQN, to L2 memory.   

      in order to reduce the latency, in the existing design 4 JESD attach design, the DFE PFIR would have to be reduced to an impulse, in a non symmetric mode.

      However the ADC32RF80 still has a decimation filter to go from 2949.12Mhz to 368.64Mhz complex that is longer than 10ns.

      Since the JESD 204 interface on the receiver buffers several frames of data, you may need a special JESD204B Rx configuration to reduce the deterministic

      latency buffering.

      Using the Signal Processing bypass in 66AK2L06, the highest receiver rate is 122.88Msps for a single chanel from the JESD204B receive to the DSP L2

      memory.   There is a design 1 plus example for the RFSDK using the 66AK2L06 available from Azcom, a third party developer.

    Regards,

    Joe Quintal