Other Parts Discussed in Thread: DRA726
I am trying to figure out how to modify the device tree for our new design.
I thought that pinmux was part of the answer but I don't see how the files generated fit into u-boot or the linux kernel.
How does that work and do you have a pinmux that supports the DRA726?
Right now I am using the am572xx evaluation board until I get our hardware. Is there a pinmux file I could use to start with that has all the current settings used in the SDK?
I found something odd, what it means is not obvious to me.
In a conf file I get this when I pick two can ports that I can use on the evaluation board. Here is for CAN1
0x4A0037D4 0x50000 G19 CTRL_CORE_PAD_DCAN1_RX dcan1_rx dcan1_rx
0x4A0037D0 0x10000 G20 CTRL_CORE_PAD_DCAN1_TX dcan1_tx dcan1_tx
In the u-boot file dra72-evm-common.dtsi I see this for CAN1
The rx pin we connect to is not listed but that what is there does reflect the first entry in the Cortex M4 code
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
In order to get the can to work on the cortex M4 we enter this according to Brad. Why do we have to
/* Wake-up dcan1_rx */
u32RegVal = HW_RD_REG32(CSL_IPU_CORE_PAD_IO_REGISTERS_REGS + 0x20000418U);
u32RegVal &= ~0x0000000F;
u32RegVal |= 0x0000000F;
HW_WR_REG32(CSL_IPU_CORE_PAD_IO_REGISTERS_REGS + 0x20000418U, u32RegVal);
/* Select default/gpio function instead of dcantx in the CORE PAD */
u32RegVal = HW_RD_REG32(CSL_IPU_CORE_PAD_IO_REGISTERS_REGS + 0x200003D0U);
u32RegVal &= ~0x0000000F;
u32RegVal |= 0x0000000F;
HW_WR_REG32(CSL_IPU_CORE_PAD_IO_REGISTERS_REGS + 0x200003D0U, u32RegVal);
/* Select default/gpio function instead of dcantx in the CORE PAD */
u32RegVal = HW_RD_REG32(CSL_IPU_CORE_PAD_IO_REGISTERS_REGS + 0x200003D4U);
u32RegVal &= ~0x0000000F;
u32RegVal |= 0x0000000F;
HW_WR_REG32(CSL_IPU_CORE_PAD_IO_REGISTERS_REGS + 0x200003D4U, u32RegVal);
The CAN code does work. Does that mean that u-boot pinmux is meaningless?
Why is the wakeup pin enabled instead of the actual pin for CAN 1 receive?
