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AM3517 26Mhz sys_clk Input Clock

Prad
Expert 1125 points
Other Parts Discussed in Thread: AM3517

 

Hi,

 

What is the reference/threshold voltage of 26Mhz sys_clk Input Clock for Duty Cycle(45% - 55%) and transition time(5ns).

 

The AM3517 Input Clock Specifications for 26 MHz mentions the Duty Cycle tw(xtalin) as 45% - 55% ,

could you please let me know what is the value of voltage threshold at which the waveform should be logic high state,

like the below figure.

 

 

Best Regards.

 

  • 0
    TI__Genius 16690 points

    Hi Prad,

    They are specified in the section "3.3 DC Electrical Characteristics" of data manual (SPRS550A). The max low level input voltage of sys_xtalin is 0.2 x VDDOSC and the min high level input voltage is 0.8 x VDDOSC.

    Regards,

    Kazunobu Shin

  • 0 in reply to kshin
    Expert 1125 points

    Hi Shin,

     

    Thankyou,

     

    In the above example figure, the Duty cycle is measured from 50% or 1.4V of the waveform

    and the Rise time is measured from 20% to 80% of waveform( vice versa for Fall time).

     

    Will it be same for AM3517?

    i.e. duty Cycle(45% - 55%) is measured from 50%(0.9V) of the waveform and transition time(5ns)

    is measured from 20% to 80% of the waveform?

     

    Regards.

  • 0 in reply to Prad
    TI__Genius 16690 points

    Duty cycle is measured at 50% of 1.8 V oscillator power supply (VDDOSC). The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

    Regards,

    Kazunobu Shin