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TDA2Ex EMIF: Data setup / hold time to DQS

Lloyd Hwang
Expert 3790 points

Hello Team,

My customer is using TDA2Eco in Surround View System, and is asking how to modify data (DQ) setup/hold time to DQS/DQS#.

The screen shot of DQ (green) and DQS/DQS# (yellow) is captured as following, and it shows DQS leans to one side of DQ.

Customer would like to tune the position of DQS to the center of DQ for the stable ddr3 write operation.

They tried below test, but there is no improvement.

  - When customer tried to change the value of  "EMIF_EXT_PHY_CONTROL_17~20",  waveform is not changed.

  - When customer tried to change the value of PHY_REG_WR_DQS_SLAVE_D in "EMIF_EXT_PHY_CONTROL_23", waveform is not changed.

  - When customer tried to change the value of PHY_REG_WR_DQS_SLAVE_D in "EMIF_EXT_PHY_CONTROL_23" and DLL_OVERRIDE=1, system becomes lock up.

Could you guide which register can be configured to modify  data (DQ) setup/hold time to DQS/DQS#?

If there is any procedure to configure, please let me know as well.

Thank you.

 

[Waveform - DQS/DQS# and DQ]

 

[Register - EMIF_EXT_PHY_CONTROL_23]

 

 

regards,

Lloyd Hwang

  • 0
    TI__Intellectual 2330 points
    Hi Lloyd,

    I think, you have to use the EMIF_EXT_PHY_CONTROL_25 register. It controls the skew between the write DQS and the write DQ signals. This register has 4 fields (REG_PHY_DQ_OFFSET[3:0]) each associated with an SDRAM byte lane. All fields must be loaded with same values. If you write 0x40 to each field this results in 90 degree shift between write DQS and write DQ.

    BR,
    Dobrin
  • 0 in reply to Dobrin Dobrinov
    TI__Expert 3790 points

    Hello Dobrin,

    Thanks for the feedback.

    Customer checked "EMIF_EXT_PHY_CONTROL_25" register changes the skew between the write DQS and the write DQ signals as below.

    Measuring data0 and DQS0, it shows that the skew is changing as "DQ_OFFSET" 

    Customer asked how they find the proper DQ offset at customer board.  

    It is impossible to measure all the data lane (DQ and DQS)  by changing DQ_OFFSET.  

    Competitor provides the calibration tool to find the profer DQ offset as below.

    Do we have similar tool as below?

    (p.s.  TRM says only that 0x40 is recommended with 90 degree shift, but the measurment shows that it is not the centor (90 degree).)

    regards,

    Lloyd

      

  • 0 in reply to Lloyd Hwang
    TI__Intellectual 2330 points
    Hi Lloyd,

    You measure at the SDRAM side, right? Value of 0x40 should be for 90 degree shift at SoC side and if the trace length matching requirements for DQ and DQS are met, 90 degree shift should be observed at SDRAM side but as shown on your diagram above it is approximately 45 degree shift. So, I assume this might be due to trace length mismatch between DQ and DQS.

    Another strange thing is that your first diagram from the first post looks exactly like the first one above where 0x40 is loaded to DQ_OFFSET. Have you checked the value of DQ_OFFSET before writing another values? As TI recommends 0x40 I assume that the default value for your system has also been 0x40 which would explain why both diagrams are matching.

    In addition, I'll ask if TI has some kind of calibration tool to find the proper DQS offset.

    BR,
    Dobrin
  • 0 in reply to Dobrin Dobrinov
    TI__Expert 3790 points
    Hi Dobrin,

    The First diagram from the first post is taken with the default value, which is 0x40.
    That is the reason the diagram is the same as the first diagram from second post (0x40), as you're assuming.
    Please let me know TI can provide some kind of calibration tool for proper DQS offset.
    Thanks a lot.

    Regards,
    Lloyd
  • 0 in reply to Lloyd Hwang
    TI__Intellectual 2330 points
    Hi Lloyd,

    I asked as I'm not aware if such a tool exists. There are TI EMIF tools that calculate different parameters but as far as I know they don't touch the DQ_OFFSET fields. However, I suspect the issue might be caused by propagation delay mismatches between DQS and DQ. Have your customer ensured that the DQ and DQS signals within a byte lane are:
    - propagation delay matched
    - routed on the same layer
    - have equal number of via barrels if any (better w/o vias)
    - etc.

    BR,
    Dobrin